Noah Boorstin
44606b6c19
busybear: respect branch predictor disable config
2021-04-27 15:52:18 -04:00
Noah Boorstin
ff1a6b63ed
ok but do that better
2021-04-26 14:38:05 -04:00
Noah Boorstin
0324329ed9
linux: start using internal branch predictor signal
2021-04-26 14:34:38 -04:00
Noah Boorstin
ee628e388a
minor busybear fixes
2021-04-26 13:24:39 -04:00
Ross Thompson
8e5409af66
Icache integrated!
...
Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
bbracker
1cc0dcc83f
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
bbracker
86946266cf
thomas fixed it before I did
2021-04-24 09:38:52 -04:00
bbracker
a3487a9e47
do script refactor
2021-04-24 09:32:09 -04:00
Thomas Fleming
e3672ca23f
Add address translation to busybear testbench
2021-04-23 20:12:20 -04:00
Noah Boorstin
09755251bc
busybear
2021-04-23 17:32:37 -04:00
Noah Boorstin
cd7ea29ce6
buildroot: add workaround for weird initial MSTATUS state
2021-04-21 16:03:42 -04:00
Noah Boorstin
3f0ead9d4e
yay buildroot passes a decent amount of tests now
...
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
2021-04-19 03:26:08 -04:00
Noah Boorstin
2af4e2f4ac
slowly more buildroot progress
2021-04-18 18:18:07 -04:00
Noah Boorstin
9bb1233433
neat verilog thing
2021-04-18 17:48:51 -04:00
Noah Boorstin
6954e6df4c
buildroot: sim is now running!
...
yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
4f97e9e761
start to add buildroot testbench
...
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
Thomas Fleming
3c49fd08f6
Remove imem from testbenches
2021-04-14 20:20:34 -04:00
Noah Boorstin
d66fcbc4ab
busybear: use (slightly) less terrible verilog
2021-04-14 00:18:44 -04:00
Noah Boorstin
c75455cc41
busybear testbench updates
...
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic
I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
2021-04-14 00:00:27 -04:00
Noah Boorstin
14d2ad1e2d
try to remove git-lfs stuff
2021-04-08 13:23:11 -04:00
Noah Boorstin
284d583877
add busybear boot files with git-lfs
2021-04-05 19:38:43 -04:00
Noah Boorstin
0e3f013212
busybear: reenable 'ruthless' CSR checking
2021-04-05 12:53:30 -04:00
Noah Boorstin
f4e5642c62
busybear: temporary stop after 800k instrs
2021-04-03 21:37:57 -04:00
Noah Boorstin
75f58c4df5
busybear: temporarially stop checking CSRs
2021-03-31 14:14:32 -04:00
Noah Boorstin
118e846ef7
busybear: clean up questa warnings
2021-03-31 14:04:57 -04:00
ushakya22
6b9ae41302
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
Noah Boorstin
d02c88dab5
busybear: stop NOPing out atomics
...
and bump regression to check for 800k instrs, up from 200k
2021-03-25 13:29:56 -04:00
Noah Boorstin
849641f31e
busybear: add better warning on illegal instruction
...
...also it seems that mret is being picked up as an illegal instruction??
2021-03-22 18:24:35 -04:00
Noah Boorstin
34b8f750ce
busybear: temporarially force rf[5] correct after failure to read CSR
2021-03-22 18:12:41 -04:00
Noah Boorstin
77dd0b4504
busybear: allow overwriting read values
2021-03-22 17:28:44 -04:00
Noah Boorstin
7bb31c3287
busybear: finally get the right error
2021-03-22 16:52:22 -04:00
Noah Boorstin
2aa76b27e1
busybear: comment out some debug printing
2021-03-22 14:54:05 -04:00
Noah Boorstin
74bcd9b994
regression: expect 200k instead of 100k busybear instrs
...
and a minor busybear bugfix
2021-03-22 14:47:52 -04:00
Shreya Sanghai
09faa40eb6
fixed minor bugs in testbench
2021-03-18 17:37:10 -04:00
Noah Boorstin
bfa7aedd35
busybear: add seperate message on bad memory access becasue its confusing
2021-03-16 21:42:26 -04:00
Noah Boorstin
400791163e
copy Ross's branch predictor preload change into busybear
2021-03-15 18:27:27 -04:00
Noah Boorstin
a8b242a6ef
busybear: account for CSR moving
2021-03-11 06:45:14 +00:00
Noah Boorstin
4a8b689f62
busybear: better NOPing out of float instructions
2021-03-08 21:24:19 +00:00
Noah Boorstin
c780a25f92
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
Noah Boorstin
93c9c57426
busybear: load mem files from verilog instead of .do
2021-03-08 19:26:26 +00:00
Noah Boorstin
1a11b60664
busybear: slight testbench update
2021-03-05 19:00:40 +00:00
Noah Boorstin
62b441f3f5
busybear: probably discovered bug in ahb code
2021-03-01 20:56:04 +00:00
Noah Boorstin
965d48afe7
busybear: only check pc when it actually changes
2021-03-01 19:08:35 +00:00
Noah Boorstin
4833b36535
busybear: more adapting to new memory system
2021-03-01 18:50:42 +00:00
Noah Boorstin
db86d20d11
busybear: check instead of providing InstrF
2021-02-28 16:46:53 +00:00
Noah Boorstin
e5e345d161
busybear: instantiate normal wallypipelinedsoc
2021-02-28 06:02:21 +00:00
Noah Boorstin
ab9247d625
busybear: add main ram loading, better instr checking also
2021-02-26 20:26:54 +00:00
kaveh Pezeshki
ad631ec3a1
fixed sensitivity list on error checking always block, removed useless once and for all
2021-02-26 13:41:16 -05:00
kaveh pezeshki
d32421822c
restored
2021-02-26 02:22:08 -08:00
kaveh pezeshki
3bb8e0d918
condensed always blocks to avoid race conditions
2021-02-24 11:35:28 -08:00
