DTowersM
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3f7eddbc89
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working makefile for embench and removed testbench-f64
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2022-05-26 00:08:18 +00:00 |
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David Harris
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412d4656ed
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Zero'd wfiM when ZICSR not supported to fix hang in E tests
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2022-05-05 15:32:13 +00:00 |
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David Harris
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7f42ff06d2
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SFENCE.VMA should be illegal in user mode
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2022-05-05 15:15:02 +00:00 |
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David Harris
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f436e93fc5
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SFENCE.VMA should be illegal in user mode
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2022-05-05 14:59:52 +00:00 |
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David Harris
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9b7aab122e
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wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
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2022-05-05 14:37:21 +00:00 |
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David Harris
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1a7599ce94
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Changed WFI to stall pipeline in memory stage
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2022-05-05 02:03:44 +00:00 |
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Kip Macsai-Goren
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b155effe66
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put privileged tests back into rv32/64gc
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2022-05-04 21:20:25 +00:00 |
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Kip Macsai-Goren
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895a4f4832
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updated makefrag and tests.vh to reflect removed tests, new names
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2022-05-04 21:20:25 +00:00 |
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David Harris
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8a43d6099b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-03 18:32:04 +00:00 |
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David Harris
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4b91fddc0a
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Illegal instruction fault when running FPU instruction with STATUS_FS = 0
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2022-05-03 18:32:01 +00:00 |
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David Harris
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3efbd2565a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-03 08:53:35 -07:00 |
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David Harris
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20bbe43a23
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clean up sram1p1rw; still doesn't work on Modelsim 2022.1
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2022-05-03 08:31:54 -07:00 |
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David Harris
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1166c40059
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FPU generates illegal instruction if MSTATUS.FS = 00
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2022-05-03 11:56:31 +00:00 |
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David Harris
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bcd8728b3e
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Switched to behavioral comparator for best PPA
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2022-05-03 11:00:39 +00:00 |
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David Harris
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b4a422f771
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Comparator experiments
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2022-05-03 10:54:30 +00:00 |
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David Harris
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057524b840
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Formatting cache.sv
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2022-05-03 10:53:20 +00:00 |
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David Harris
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9e50c3440d
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sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera
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2022-05-03 03:50:41 -07:00 |
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David Harris
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0df73d203b
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Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.
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2022-05-03 03:45:41 -07:00 |
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David Harris
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9e47fca2b7
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Changed loop variable in CLINT because of error only seen on VLSI
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2022-05-03 10:10:28 +00:00 |
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Kip Macsai-Goren
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75e90f193e
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added missing SIE test
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2022-04-29 19:54:29 +00:00 |
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Kip Macsai-Goren
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c0b56bfd27
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renamed PIE-stack tests to status-mie for clarity
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2022-04-29 18:30:39 +00:00 |
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Kip Macsai-Goren
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c47ec36bc7
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removed old unused tests from wally arch tests
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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746fcfde30
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set WFI timeout to after 16 bits of counting for all configs
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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aedf0341af
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added 32 bit versions of new tests. all but timeout wait pass regression
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2022-04-28 18:14:07 +00:00 |
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Skylar Litz
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64a537c59b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-27 10:50:19 -07:00 |
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Skylar Litz
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f2b6842edb
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fix AttemptedInstructionCount from ground zero
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2022-04-27 10:45:40 -07:00 |
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David Harris
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515270a8cf
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Added torture.tv test vectors
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2022-04-27 13:08:36 +00:00 |
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David Harris
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cce0a421be
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Checked in torture.tv
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2022-04-27 13:06:24 +00:00 |
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David Harris
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9d82232c14
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Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv
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2022-04-26 19:41:30 +00:00 |
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Kip Macsai-Goren
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4b00531d77
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fixed incorrect configs in regression
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2022-04-25 19:28:47 +00:00 |
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Kip Macsai-Goren
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74b103fae4
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added working tests to test list, updated regression for new configs
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2022-04-25 19:18:15 +00:00 |
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Kip Macsai-Goren
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33875b20b5
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fixed initial value, timing on fs bits changing after floating point instruction
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2022-04-25 19:17:29 +00:00 |
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Kip Macsai-Goren
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2e0f45eab4
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removed atomic, floating point from privileged tests configs
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2022-04-25 19:13:15 +00:00 |
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Kip Macsai-Goren
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01f8bdfafc
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added new tests to tests.vh, comented out until they pass regression
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2022-04-25 18:22:44 +00:00 |
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Kip Macsai-Goren
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992cedbc52
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Lowered WFI timeout wait time for privileged configs
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2022-04-25 17:47:10 +00:00 |
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David Harris
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0957b7040d
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Restored MPRV behavior per spec
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2022-04-25 14:52:18 +00:00 |
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David Harris
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1a8369b02b
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Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields
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2022-04-25 14:49:00 +00:00 |
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David Harris
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142636173e
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Added MTINST hardwired to 0, and added timeout of U-mode WFI
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2022-04-24 20:00:02 +00:00 |
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David Harris
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28e8aa4f97
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Fixed InstrMisalignedFaultM mtval
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2022-04-24 17:31:30 +00:00 |
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David Harris
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ffecdda6e6
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Improved priority order and mtval of traps to match spec
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2022-04-24 17:24:45 +00:00 |
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David Harris
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04b0579b89
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Extended sim time to fully boot Linux. Added comments to hazard unit
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2022-04-24 13:51:00 +00:00 |
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Kip Macsai-Goren
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bd87af478a
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Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
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2022-04-22 22:46:11 +00:00 |
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bbracker
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9eec1a83a6
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deprecate unused LINUX_FIX_READ macro
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2022-04-21 19:14:47 -07:00 |
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bbracker
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9c1e398bb5
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change how tristate I/O is spoofed in GPIO loopback test
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2022-04-21 10:31:16 -07:00 |
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Ross Thompson
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e56b9f18d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-21 09:52:42 -05:00 |
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Ross Thompson
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a86274a1e0
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Modified wally-pipelined.do for no trace linux sim.
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2022-04-21 09:52:33 -05:00 |
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David Harris
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1e19cf9f14
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Simplified profile for UART boot; added warnings on UART Rx errors
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2022-04-21 04:54:45 +00:00 |
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Kip Macsai-Goren
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25d0f6305a
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added new tests to tests.vh
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2022-04-20 17:34:40 +00:00 |
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Kip Macsai-Goren
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8e72ace5ac
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fixed rv32ia to support clint and GPIO for priv tests
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2022-04-20 17:31:34 +00:00 |
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Kip Macsai-Goren
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324d3fcea5
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added working general trap tests to regression
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2022-04-20 06:48:01 +00:00 |
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