David Harris
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865d5ce0b1
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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David Harris
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ecce1e62ee
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changed ideal memory to MEM_DTIM and MEM_ITIM
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2021-12-14 13:05:32 -08:00 |
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David Harris
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8dcf2c65f2
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renamed rv32/64g to rv32/64gc in configuration
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2021-12-14 11:22:00 -08:00 |
|
Ross Thompson
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4cea8d1a29
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Performance counters now output of coremark.
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2021-12-09 14:48:17 -06:00 |
|
Ross Thompson
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500e6ff430
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Fixed buildroot to work with the fpga's merge.
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2021-12-02 18:09:43 -06:00 |
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Ross Thompson
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b03ca464f1
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Mostly integrated FPGA flow into main branch. Not all tests passing yet.
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2021-12-02 18:00:32 -06:00 |
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Ross Thompson
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a871118116
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Merge branch 'main' into fpga
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2021-11-29 10:10:37 -06:00 |
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Ross Thompson
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5642918ead
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Merge branch 'main' into fpga
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2021-11-29 10:06:53 -06:00 |
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Ross Thompson
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3fc370654d
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Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation.
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2021-11-23 10:00:32 -06:00 |
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Ross Thompson
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f4c221f20a
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Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
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2021-11-17 12:47:19 -06:00 |
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Ross Thompson
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23e78c4842
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Fixed uart by reversing the bit order on transmit.
Set prescale to 0.
|
2021-11-17 10:32:41 -06:00 |
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bbracker
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526aff54a8
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linux testgen refactor
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2021-11-01 14:09:49 -07:00 |
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Ross Thompson
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77e2b6f9a9
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Merge branch 'main' into fpga
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2021-10-22 16:09:16 -05:00 |
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kipmacsaigoren
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ef297067e9
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removed reduntant definitions for FPU in MISA.
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2021-10-22 15:18:25 -05:00 |
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Ross Thompson
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de4ea16d32
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Merge branch 'main' into fpga
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2021-10-20 16:24:55 -05:00 |
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Shreya Sanghai
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4424006624
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added DESIGN_COMPLIER to forgotten config files
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2021-10-12 10:14:04 -07:00 |
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Ross Thompson
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f6c6cb9ed2
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Merge branch 'main' into fpga
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2021-10-11 18:17:58 -05:00 |
|
Shreya Sanghai
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0acf9fd746
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made redunantmul generate DW02_multp for synopsys sythnesis
|
2021-10-11 11:54:39 -07:00 |
|
Ross Thompson
|
9150133c7d
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Fpga simualtion files.
|
2021-10-11 10:24:40 -05:00 |
|
Ross Thompson
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bfe633d087
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Partially working sd card reader.
|
2021-10-11 10:23:45 -05:00 |
|
David Harris
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75c17dc372
|
Major reorganization of regression and simulation and testbenches
|
2021-10-10 15:07:51 -07:00 |
|
David Harris
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48e33c79a9
|
Reduced cycle count for DIVW/DIVUW by two
|
2021-10-03 09:42:22 -04:00 |
|
David Harris
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2ae51d1852
|
Parameterized number of bits per cycle for integer division
|
2021-10-03 01:10:15 -04:00 |
|
Ross Thompson
|
7ca801113e
|
Added debugging directives to system verilog.
|
2021-09-27 13:57:46 -05:00 |
|
Ross Thompson
|
44196af61a
|
Have program which checks for sdc init and issues read, but read done is
not correctly being read back by the software. The error is in how the
sdc indicates busy.
|
2021-09-24 15:53:38 -05:00 |
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Ross Thompson
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80e37d2291
|
Added SDC defines to each config mode.
Added sd_top which is the sd card reader.
|
2021-09-24 12:24:30 -05:00 |
|
Ross Thompson
|
fea439b84d
|
SDC to ABHLite interface partially done.
Added SDC to adrdec and uncore.
|
2021-09-24 10:45:09 -05:00 |
|
David Harris
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9ae25b0cea
|
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
|
2021-09-15 13:14:00 -04:00 |
|
Ross Thompson
|
570aab4275
|
Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.
|
2021-09-11 15:40:27 -05:00 |
|
Ross Thompson
|
86fbe2a654
|
Changed configs to support 4 ways set associative caches.
|
2021-09-08 12:52:49 -05:00 |
|
Ross Thompson
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6550f38af9
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-09-08 12:47:03 -05:00 |
|
Ross Thompson
|
49e75d579c
|
Set associate icache working, but way 0 is never written.
|
2021-09-07 12:46:16 -05:00 |
|
Katherine Parry
|
70f332fe2f
|
FMA cleanup
|
2021-08-28 10:53:35 -04:00 |
|
Katherine Parry
|
aedd71d570
|
move some FPU select muxs to execute stage
|
2021-08-13 14:41:22 -04:00 |
|
Katherine Parry
|
e00f181bcf
|
LZA added to FMA and attemting a merged FMA and adder in synthesis
|
2021-08-10 13:57:16 -04:00 |
|
Ross Thompson
|
c749d08542
|
fixed the read timer issue but we still have problems with interrupts and i/o devices.
|
2021-08-06 10:16:06 -05:00 |
|
Katherine Parry
|
ef28679721
|
fpu cleanup
|
2021-07-24 14:59:57 -04:00 |
|
bbracker
|
d3059dd04c
|
fix UART RX FIFO bug where tail pointer can overtake head pointer
|
2021-07-22 02:09:41 -04:00 |
|
Katherine Parry
|
b9081e514c
|
FMA parameterized
|
2021-07-20 22:04:21 -04:00 |
|
David Harris
|
1f3dfa20f6
|
flag for optional boottim
|
2021-07-20 14:46:37 -04:00 |
|
David Harris
|
e1a1a8395e
|
Parameterized I$/D$ configurations and added sanity check assertions in testbench
|
2021-07-20 08:57:13 -04:00 |
|
Ross Thompson
|
508c3e35af
|
Restored TIM range.
|
2021-07-19 21:17:31 -05:00 |
|
David Harris
|
4d40b5faef
|
Added cache configuration to config files
|
2021-07-19 18:19:46 -04:00 |
|
David Harris
|
46ab609498
|
Updated FMA1 with parameterized size
|
2021-07-18 20:40:49 -04:00 |
|
David Harris
|
4f8f52f283
|
Added FLEN, NE, NF to config and started using these in FMA1
|
2021-07-18 17:28:25 -04:00 |
|
David Harris
|
8d348dacce
|
Started atomics
|
2021-07-17 21:11:41 -04:00 |
|
David Harris
|
1bd5c137a6
|
Reduced size of physical memory by 16 for performance
|
2021-07-16 20:10:12 -04:00 |
|
Ross Thompson
|
6521d2b468
|
Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
|
2021-07-16 14:21:09 -05:00 |
|
Ross Thompson
|
1aabee0478
|
Updated the config so the tim has a bigger range.
|
2021-07-16 12:35:00 -05:00 |
|
Katherine Parry
|
c74d26eea4
|
Fixed lint warning
|
2021-07-14 21:24:48 -04:00 |
|