Kip Macsai-Goren
|
3c6b856068
|
Added cause_s_soft_from_m_interrupt
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2023-03-24 11:22:39 -07:00 |
|
Kip Macsai-Goren
|
3ce82f93c0
|
added premilinary boundary ccrossing cases
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2023-03-24 11:22:39 -07:00 |
|
Kip Macsai-Goren
|
5c3f5fe8c6
|
added in the CSR name for stimecmp(h)
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2023-03-04 15:53:03 -08:00 |
|
Kip Macsai-Goren
|
4fa78a02b7
|
removed changes to counteren from stimecmp tests
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2023-03-04 15:46:57 -08:00 |
|
Kip Macsai-Goren
|
da9627708e
|
Added correct causing and handling of S time interrupts to test suite.
|
2023-03-04 15:04:17 -08:00 |
|
David Harris
|
fe0a893182
|
Renamed section 12.3 to 8.3 in MMU test definitions
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2023-02-19 05:46:46 -08:00 |
|
David Harris
|
8b34f5ac98
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-01-28 18:18:53 -08:00 |
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Kip Macsai-Goren
|
95b26c49b9
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Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts.
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2023-01-28 17:29:35 -08:00 |
|
David Harris
|
71d1c8fc68
|
Removed unused WALLY test references
|
2023-01-27 07:25:04 -08:00 |
|
David Harris
|
ae7d23380a
|
Removed unused reference files
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2023-01-27 07:21:55 -08:00 |
|
Kip Macsai-Goren
|
ffae1c5ee6
|
added fs=00 to status fp enabled test
|
2022-12-22 15:15:53 -08:00 |
|
Kip Macsai-Goren
|
a768d70093
|
Added status.tvm bit test that passes make and regression
|
2022-12-22 14:43:22 -08:00 |
|
Kip Macsai-Goren
|
7aadf50f26
|
updated trap handler alignemnts to 64 bytes in priv tests
|
2022-12-22 14:23:04 -08:00 |
|
David Harris
|
c7f3aae084
|
Only delegated bits of SIP are readable
|
2022-12-21 12:32:49 -08:00 |
|
Ross Thompson
|
c3b43b2fac
|
Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
|
2022-12-21 13:16:09 -06:00 |
|
Ross Thompson
|
0b4186f1e8
|
Vectored interrupts now require 64 byte alignment.
Eliminates adder.
|
2022-12-21 12:05:49 -06:00 |
|
Kip Macsai-Goren
|
2dfa426e10
|
added passing GPIO test to 64 bit tests
|
2022-12-05 21:31:00 -08:00 |
|
Kip Macsai-Goren
|
1d268fded4
|
added corrrect scr read out of uart to periph test
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
7411d50a78
|
added all 32 bit tests to 64 bit periph tests except gpio
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
badc684f07
|
added copies of 64 bit tests to 32 bit periph and priv tests
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
282d06b45f
|
added -01 to all WALLY tests
|
2022-12-05 20:16:02 -08:00 |
|
Kip Macsai-Goren
|
af00eadec2
|
added tests for invalid address being written to satp. Not passing regression
|
2022-11-27 13:22:35 -08:00 |
|
Kip Macsai-Goren
|
6fdd603ba1
|
added potential fix to overrun error and fifo interrupt error. test passes
|
2022-11-06 22:01:02 -08:00 |
|
Kip Macsai-Goren
|
b42fc7ec6d
|
fixed fifo timout handling. error now in data ready interrupt
|
2022-11-05 13:34:24 -07:00 |
|
Kip Macsai-Goren
|
23268d22e5
|
fixed broken instructions so make works.
|
2022-11-03 23:06:20 +00:00 |
|
Ross Thompson
|
f81d1e15b6
|
More outline for uart timeout interrupt.
|
2022-10-28 13:53:56 -05:00 |
|
Ross Thompson
|
372b9890ef
|
Untested change to uart test for outline of how to handle rx fifo timeout.
|
2022-10-28 13:31:16 -05:00 |
|
Kip Macsai-Goren
|
d4dd2dcc08
|
Added test for UART FIFO timeout. Does not pass regression
|
2022-10-25 05:35:56 +00:00 |
|
Kip Macsai-Goren
|
d5cd67cf09
|
fixed endianness mstatush problem, passes make, not regression
|
2022-10-04 17:37:39 +00:00 |
|
Kip Macsai-Goren
|
0d2fcaeab1
|
added xlen and endianness test edits. xlen passes but endinanness still won't make
|
2022-09-26 05:03:19 +00:00 |
|
Kip Macsai-Goren
|
3f4c825a1a
|
added mstatus uxl, sxl bit tests (not tested in regression yet)
|
2022-09-18 00:11:29 +00:00 |
|
Kip Macsai-Goren
|
dda3b2d383
|
ported endianness tests to 32 bits (not tested in regression yet)
|
2022-09-18 00:10:29 +00:00 |
|
Kip Macsai-Goren
|
99596fac84
|
Fixed typos in existing endianness test
|
2022-09-18 00:09:52 +00:00 |
|
Kip Macsai-Goren
|
657e19df08
|
added full coverage of subword loads and stores to endianness test
|
2022-09-17 23:14:38 +00:00 |
|
Kip Macsai-Goren
|
a4fc5d3476
|
Created initial endianness tests
|
2022-09-16 01:06:26 +00:00 |
|
David Harris
|
8b8f045491
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
|
2022-08-03 09:33:56 -07:00 |
|
David Harris
|
62252c2167
|
Debugging plic-s test
|
2022-08-03 13:21:09 +00:00 |
|
David Harris
|
6ee8036ae7
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
e3ea86f984
|
Started plic-s tests
|
2022-08-03 03:48:08 +00:00 |
|
David Harris
|
d2de84a456
|
Added parity and stop bit tests to UART
|
2022-07-28 04:35:51 +00:00 |
|
David Harris
|
763a6d7340
|
Fixed UART reference output
|
2022-07-27 22:16:38 +00:00 |
|
David Harris
|
f61f0645fe
|
Finished UART test
|
2022-07-27 04:06:59 +00:00 |
|
slmnemo
|
a32698811d
|
Updated reference file for UART test
|
2022-07-26 09:39:31 -07:00 |
|
slmnemo
|
528dfd9170
|
Committing changes made to UART test
|
2022-07-26 09:14:40 -07:00 |
|
slmnemo
|
5b71ceac5c
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-22 17:13:38 -07:00 |
|
slmnemo
|
0bfc3fda1b
|
Fixed UART FIFO bugs and added FIFO tests
|
2022-07-22 17:13:19 -07:00 |
|
Daniel Torres
|
e02c67ed5e
|
fixed 32priv tests, now passing
|
2022-07-22 15:35:20 -07:00 |
|
Daniel Torres
|
d95b266d49
|
changes to test.vh for compatability
|
2022-07-22 15:00:48 -07:00 |
|
Daniel Torres
|
2bbfd67082
|
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
|
2022-07-22 14:58:55 -07:00 |
|
slmnemo
|
840c40a7ab
|
UART updates and PMA fix
|
2022-07-22 14:49:03 -07:00 |
|