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237 Commits

Author SHA1 Message Date
David Harris
42d573be57 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
David Harris
12bd351edf Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
Ross Thompson
86fc632790 Moved data path logic from icacheCntrl to icache. 2021-08-26 10:58:19 -05:00
Ross Thompson
e9a1dc90f6 Removed generate around the dcache memories. 2021-08-25 13:27:26 -05:00
Ross Thompson
74fba4bb06 Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
Kip Macsai-Goren
3008111bcd added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet 2021-07-23 16:02:42 -04:00
Kip Macsai-Goren
381a93b45b added sfence to legal instructions, zeroed out rom file to populate for tests 2021-07-23 15:55:08 -04:00
Kip Macsai-Goren
52faa22774 include SFENCE.VMA in legal instructions 2021-07-22 20:24:24 -04:00
David Harris
21a65f45cd Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken. 2021-07-22 14:18:27 -04:00
Katherine Parry
01f0b4e5df FDIV and FSQRT work 2021-07-21 14:08:14 -04:00
Katherine Parry
b9081e514c FMA parameterized 2021-07-20 22:04:21 -04:00
David Harris
1f3dfa20f6 flag for optional boottim 2021-07-20 14:46:37 -04:00
David Harris
e1a1a8395e Parameterized I$/D$ configurations and added sanity check assertions in testbench 2021-07-20 08:57:13 -04:00
Katherine Parry
c9180f4ebd FDIV and FSQRT passes when simulating in modelsim 2021-07-18 23:00:04 -04:00
Katherine Parry
60dabb9094 fdivsqrt inegrated, but not completley working 2021-07-18 14:03:37 -04:00
Ross Thompson
14220684b6 Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue. 2021-07-17 21:02:24 -05:00
David Harris
8d348dacce Started atomics 2021-07-17 21:11:41 -04:00
David Harris
87aa527de7 hptw: minor cleanup 2021-07-17 13:40:12 -04:00
David Harris
ef63e1ab52 hptw: factored pregen 2021-07-17 11:11:10 -04:00
David Harris
dac22d5016 Removed more unused signals from ahblite 2021-07-17 02:21:54 -04:00
Kip Macsai-Goren
d10fd25c33 included virtual memory tests in testbench 2021-07-16 17:57:24 -04:00
Ross Thompson
6521d2b468 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
e5d624c1fa Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
b9902b0560 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. 2021-07-15 11:00:42 -05:00
Ross Thompson
704f4f724e dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
ba1e1ec231 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
c74d26eea4 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
2c946a282f Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Ross Thompson
e91501985c Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
3e57c899a2 Partially working changes to support uncached memory access. Not sure what CommitedM is. 2021-07-13 17:24:59 -05:00
Katherine Parry
efdec72df1 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
Ross Thompson
3951eb56f5 Modularized the shadow memory to reduce performance hit. 2021-07-13 10:55:57 -05:00
Ross Thompson
e594eb540d Got the shadow ram cache flush working. 2021-07-13 10:03:47 -05:00
Ross Thompson
49f6eec579 Team work on solving the dcache data inconsistency problem. 2021-07-12 23:46:32 -05:00
Ross Thompson
ecc9b5006e Now updates the dtim with the dirty data in the dcache. 
Simulation is showing issues.  It lookslike the cache is not
evicting the correct data.
 2021-07-12 15:13:27 -05:00
Ross Thompson
1cc258ade1 Progress towards the test bench flush. 2021-07-12 14:22:13 -05:00
Katherine Parry
36f59f3c99 Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
bbracker
d3dd70e3e6 more completely uncomment MMU tests to make sim wally work 2021-07-06 14:33:52 -04:00
Kip Macsai-Goren
20cd0e208b added new mmu tests to makefrag and commented out in the testbench 2021-07-05 10:54:30 -04:00
David Harris
5f91b339aa Added F_SUPPORTED flag to disable floating point unit when not in MISA 2021-07-05 10:30:46 -04:00
David Harris
9645b023c9 Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
Katherine Parry
7e3483b283 FPU forwarding reworked pt.1 2021-06-24 18:39:18 -04:00
Katherine Parry
8eed89616c fpu clean-up 2021-06-23 16:42:40 -04:00
Katherine Parry
353a27f12f rv64f FLW passes imperas tests 2021-06-22 16:36:16 -04:00
David Harris
7930c2ebb4 Commented out 100k tests to improve speed 2021-06-21 01:43:18 -04:00
Katherine Parry
2b67f25683 all rv64f instructions except convert, divide, square root, and FLD pass 2021-06-20 20:24:09 -04:00
David Harris
35c74348a4 allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
01d6ca1e2a Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
bbracker
cc91c774a6 Ah big ole merge! Passes sim-wally-batch and linting, so should be fine 2021-06-08 12:41:25 -04:00