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39efadf2cf
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406 Commits

Author SHA1 Message Date
bbracker
39efadf2cf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
bbracker
8c4e6baf48 change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros 2021-10-25 12:25:32 -07:00
David Harris
2bf51362e2 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
bbracker
13763b002a switch linux graphical sim over to Ross's waves 2021-10-24 18:39:23 -07:00
bbracker
c0a7b12f94 or actually needed to reduce expectations of buildroot 2021-10-24 06:59:34 -07:00
bbracker
d3969bb1ba increase regression's expectations of buildroot 2021-10-24 06:50:22 -07:00
bbracker
e0b6566cbd buildroot do scripts now compile flops 2021-10-23 23:14:59 -07:00
bbracker
de6a52f6eb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 13:17:37 -07:00
bbracker
3c0b0987d2 add option for regression to do a partial execution of buildroot 2021-10-23 13:17:30 -07:00
David Harris
200eb453fb wrapping up lint cleanup; many unused signals removed 2021-10-23 12:15:14 -07:00
David Harris
ac1b1bfbb6 update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
David Harris
e2e950ac0f Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
3249d65209 Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
James E. Stine
1dba57dce7 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
bbracker
4abc6fc915 change infrastructure to expect only 6.3 million from buildroot 2021-10-12 10:41:15 -07:00
David Harris
4139f27d10 Divider FSM simplification 2021-10-10 22:24:14 -07:00
David Harris
75c17dc372 Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
bbracker
13352eccda Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 13:12:44 -07:00
bbracker
161767cddd make regression expect what buildroot is actually able to reach 2021-10-10 13:12:36 -07:00
David Harris
c2bb0324c6 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
bbracker
55f6584e62 update wave-do 2021-10-07 19:16:52 -04:00
James E. Stine
199ce88b39 Add generic wave command file 2021-10-06 13:17:49 -05:00
James E. Stine
93668b5185 Update to testbench for FP stuff 2021-10-06 13:16:38 -05:00
David Harris
78eba19a1f Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
c690a863b5 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
David Harris
b3bded9e6c Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
f913305993 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
4926ae343a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
852eb24731 Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
42d573be57 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
Ross Thompson
221dbe92b2 Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
Ross Thompson
e16c27225b Finished adding the d cache flush. Required ensuring the write data, address, and size are 
correct when transmitting to AHBLite interface.
 2021-09-17 13:03:04 -05:00
Ross Thompson
0b1e59d075 Updated Dcache to fully support flush. This appears to work. 
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
 2021-09-17 10:25:21 -05:00
Ross Thompson
615fd41e7b Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. 2021-09-16 18:32:29 -05:00
Ross Thompson
cae350abb7 Added invalidate to icache. 2021-09-16 16:15:54 -05:00
bbracker
a158558b83 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-15 17:31:11 -04:00
bbracker
ff5379fd95 fix regression 2021-09-15 17:30:59 -04:00
David Harris
9ae25b0cea Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
David Harris
9fa048980d Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 2021-09-13 12:40:40 -04:00
David Harris
7be1160a48 Cleaned up wally-arch test scripts 2021-09-13 00:02:32 -04:00
David Harris
12bd351edf Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
David Harris
9480f8efdb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-08 16:00:12 -04:00
David Harris
118cb7fb87 Added testbench-arch for riscv-arch-test suite 2021-09-08 15:59:40 -04:00
Ross Thompson
6550f38af9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-08 12:47:03 -05:00
Ross Thompson
a15d6c1c96 Slight modification to wave file. 2021-09-08 10:40:46 -05:00
bbracker
bb84354a47 fixed bug where M mode was sensitive to S mode traps 2021-09-07 19:14:39 -04:00
bbracker
da9a366d20 No longer forcing CSRReadValM because that can feedback to corrupt some CSRs 2021-09-06 22:59:54 -04:00
Ross Thompson
05455f8392 Changed name of memory in icache. 2021-09-06 20:54:52 -05:00
bbracker
c463f177e9 restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair 2021-09-04 19:45:04 -04:00
Ross Thompson
2968623f9a Partial multiway set associative icache. 2021-08-30 10:49:24 -05:00