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Author SHA1 Message Date
Kip Macsai-Goren
9566daccaa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-03 16:32:27 -04:00
Kip Macsai-Goren
2524e05765 mmu test fully compiles and produces correct ovpsim outputs. regression is as of yet untested. 2021-07-03 16:32:04 -04:00
Ben Bracker
d8facacef6 src/cache/ICacheCntrl.sv 2021-07-03 11:24:41 -05:00
Ben Bracker
eff5a1b90f fix ICache indenting 2021-07-03 11:11:07 -05:00
David Harris
1fa4abf7b6 Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker 2021-07-03 03:29:33 -04:00
David Harris
d44916dacf Cleaned up PMA/PMP checker unused code 2021-07-03 02:25:31 -04:00
Ben Bracker
59b177beac stop busybear from hanging 2021-07-02 17:22:09 -05:00
David Harris
0bd18ff662 Fixed PMPCFG read faults 2021-07-02 17:08:13 -04:00
Ross Thompson
cf688bd3f6 Fixed up the physical address generation for 64 bit page table walker. 2021-07-02 15:49:32 -05:00
Ross Thompson
8e3149517a Fixed up the bit widths on the page table walker for rv32. 2021-07-02 15:45:05 -05:00
Ross Thompson
7b3716c281 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-02 13:56:49 -05:00
Katherine Parry
20d6e57aa5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-02 12:56:53 -04:00
Katherine Parry
308c9ccaac FPU update - missing files 2021-07-02 12:53:05 -04:00
Ross Thompson
dbd33465e1 Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
David Harris
5b6ebd7935 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-02 12:52:20 -04:00
Katherine Parry
30ff212ca8 FPU update 2021-07-02 12:40:58 -04:00
David Harris
76a43eb468 Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:05:25 -04:00
David Harris
c85e0df1ff Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:04:13 -04:00
Ross Thompson
d1a366472f reverted change to the imperas tests order. Accidently commited change which placed the virtual memory tests first. 2021-07-01 18:04:43 -05:00
Ross Thompson
118dfa9cec added page table walker fault exit for icache. 2021-07-01 17:59:55 -05:00
Ross Thompson
61027f650c OMG. It's working! 2021-07-01 17:37:53 -05:00
Ross Thompson
6916784354 Fixed tab space issue. 2021-07-01 17:17:53 -05:00
Ross Thompson
2dc349ea6f Fixed the wrong virtual address write into the dtlb. 2021-07-01 16:55:16 -05:00
Teo Ene
70a15afe2e Correct physical implementation flow path 2021-07-01 16:37:49 -05:00
Teo Ene
ec21126474 Flow updated for 90nm 2021-07-01 13:32:42 -05:00
Ross Thompson
88a18496cf Got some stores working in virtual memory. 2021-07-01 12:49:09 -05:00
Ross Thompson
157b1b31bf Icache ITLB interlock fix. 2021-06-30 19:24:59 -05:00
Ross Thompson
002c32d2ad The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay. 2021-06-30 17:02:36 -05:00
Ross Thompson
9ec624702d Major rewrite of ptw to remove combo loop. 2021-06-30 16:25:03 -05:00
Ross Thompson
b2d8ba6742 The icache now correctly interlocks with the PTW on TLB miss. 2021-06-30 11:24:26 -05:00
Ross Thompson
dd84f2958e Page table walker now walks the table. 
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
 2021-06-29 22:33:57 -05:00
Katherine Parry
0c2b7a1132 FPU control signals changed and FMA works 2021-06-28 18:53:58 -04:00
Ross Thompson
bc9c944ba0 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
bbracker
751e606fb7 trying out Noah and Kaveh's proposed hack for which CSRs to update for QEMU MMU bug 2021-06-26 08:30:58 -04:00
bbracker
c93b6abed2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-26 08:29:37 -04:00
bbracker
17afd9e5e8 temporarily disable PMP checking for EBU accesses. 2021-06-26 07:19:51 -04:00
bbracker
74833dc68c split intermediate GDB output file into smaller files for better debug experience 2021-06-26 07:18:26 -04:00
Ross Thompson
d80ebab941 AMO and LR/SC instructions now working correctly. 
Page table walking is not working.
 2021-06-25 15:42:07 -05:00
Abe
12eff2bc5f Updated timing functions to read from MTIME register, TICKS_PER_SEC set to 10000 so timer reads millisecs 2021-06-25 16:42:03 -04:00
Abe
2ab29c74f2 Fixed Coremark Score output printing. Also made it so that the loop that sets the iteration count increments iterations by 1 instead by increasing it by a factor of 10 each time (which was overkill for the timing that's needed to exit the loop) 2021-06-25 16:27:23 -04:00
Ross Thompson
57a7074800 Some progress. Had to change how the page table walker got it's ready. 2021-06-25 15:07:41 -05:00
Ross Thompson
b4a788c341 Working through a combo loop. 2021-06-25 14:49:27 -05:00
Ross Thompson
d6c19e73f4 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
bbracker
13cf7c0934 linux testbench now ignores HWRITE glitches caused by flush glitches 2021-06-25 09:28:52 -04:00
bbracker
5b47da21ba made testbench-linux's PCDwrong be FlushD 2021-06-25 08:15:19 -04:00
bbracker
34dbad967d ah merge; I checked and this does pass all of regression except lints 2021-06-25 07:37:06 -04:00
bbracker
192171826b changed SC M-to-E fowarding to W-to-E forwarding to improve critical path 2021-06-25 07:18:38 -04:00
Kip Macsai-Goren
d7e518991e Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR. 2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
ac597d78c8 Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations. 2021-06-24 19:59:29 -04:00
Katherine Parry
7e3483b283 FPU forwarding reworked pt.1 2021-06-24 18:39:18 -04:00