bbracker
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2368b58cc9
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-05-03 09:23:52 -04:00 |
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Noah Boorstin
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b32128465c
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busybear: remove now unneeded hack for fixed CSR issue
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2021-05-01 15:17:04 -04:00 |
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Katherine Parry
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db95151d8d
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fpu imperas tests run
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2021-05-01 02:18:01 +00:00 |
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bbracker
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1fcd43e844
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-30 06:26:35 -04:00 |
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bbracker
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182bfdbb0e
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rv32 plic test and lint fixes
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2021-04-30 06:26:31 -04:00 |
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Domenico Ottolia
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d03ca20dc9
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Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
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2021-04-29 20:42:14 -04:00 |
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Ross Thompson
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818c0abc89
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Fixed memory size in configs for rv32ic and rv64ic.
Removed warning on call to $fscanf.
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2021-04-29 17:36:46 -05:00 |
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Domenico Ottolia
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c60c4f4adc
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Minor improvements to scause test
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2021-04-29 16:48:07 -04:00 |
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Domenico Ottolia
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c8a81779ca
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Add machine-mode timer interrupts to mcause tests
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2021-04-29 16:39:18 -04:00 |
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Domenico Ottolia
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6fc04768f5
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Same but don't break sim-wally this time
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2021-04-29 15:33:27 -04:00 |
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Domenico Ottolia
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7ae5d4d11e
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Add more exceptions to medeleg tests
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2021-04-29 15:32:13 -04:00 |
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ushakya22
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77210527c1
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Working MIE timer tests
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2021-04-29 15:19:43 -04:00 |
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Domenico Ottolia
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4fae8088e3
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Add medeleg tests
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2021-04-29 15:02:36 -04:00 |
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Noah Boorstin
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a4dad3403e
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same but do that right this time
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2021-04-28 14:27:28 -04:00 |
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Noah Boorstin
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44606b6c19
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busybear: respect branch predictor disable config
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2021-04-27 15:52:18 -04:00 |
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Ross Thompson
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8ae28e7887
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-26 14:28:09 -05:00 |
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Ross Thompson
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72363f5c66
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Added the ability to exclude branch predictor.
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2021-04-26 14:27:42 -05:00 |
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Noah Boorstin
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ff1a6b63ed
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ok but do that better
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2021-04-26 14:38:05 -04:00 |
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Noah Boorstin
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0324329ed9
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linux: start using internal branch predictor signal
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2021-04-26 14:34:38 -04:00 |
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Noah Boorstin
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ee628e388a
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minor busybear fixes
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2021-04-26 13:24:39 -04:00 |
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Ross Thompson
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8e5409af66
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Icache integrated!
Merge branch 'icache-almost-working' into main
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2021-04-26 11:48:58 -05:00 |
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bbracker
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31a0387136
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merge cleanup; mem init is broken
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2021-04-26 08:00:17 -04:00 |
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bbracker
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ba94fa3436
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it says I need to merge in order to pull
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2021-04-26 07:46:24 -04:00 |
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bbracker
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1cc0dcc83f
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progress on bus and lrsc
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2021-04-26 07:43:16 -04:00 |
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Ross Thompson
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6e803b724e
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Merge branch 'tests' into icache-almost-working
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2021-04-25 21:25:36 -05:00 |
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bbracker
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86946266cf
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thomas fixed it before I did
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2021-04-24 09:38:52 -04:00 |
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bbracker
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a3487a9e47
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do script refactor
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2021-04-24 09:32:09 -04:00 |
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Thomas Fleming
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e3672ca23f
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Add address translation to busybear testbench
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2021-04-23 20:12:20 -04:00 |
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Noah Boorstin
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09755251bc
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busybear
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2021-04-23 17:32:37 -04:00 |
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Shriya Nadgauda
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c66e63ff70
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adding pipeline testing
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2021-04-23 14:19:17 -04:00 |
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Ross Thompson
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020fb65adf
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Fixed icache for 32 bit.
Merge branch 'cache' into main
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2021-04-22 16:45:29 -05:00 |
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Thomas Fleming
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6acaa313b5
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Temporarily disable rv64 mmu test
Will restore once cache revamp is pushed
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2021-04-22 13:19:18 -04:00 |
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Noah Boorstin
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cd7ea29ce6
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buildroot: add workaround for weird initial MSTATUS state
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2021-04-21 16:03:42 -04:00 |
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Domenico Ottolia
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44da1488ff
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Add tests for stval and mtval
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2021-04-21 02:31:32 -04:00 |
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Domenico Ottolia
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f63f16f486
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Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file
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2021-04-21 01:12:55 -04:00 |
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Domenico Ottolia
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bf86a809eb
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Add tests for sepc register
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2021-04-20 23:50:53 -04:00 |
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Ross Thompson
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251ece20fe
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Broken icache. Design is done. Time to debug.
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2021-04-20 19:55:49 -05:00 |
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Noah Boorstin
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3f0ead9d4e
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yay buildroot passes a decent amount of tests now
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
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2021-04-19 03:26:08 -04:00 |
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Jarred Allen
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850f728cc7
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Merge branch 'main' into cache
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2021-04-19 00:05:23 -04:00 |
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Noah Boorstin
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2af4e2f4ac
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slowly more buildroot progress
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2021-04-18 18:18:07 -04:00 |
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Noah Boorstin
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9bb1233433
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neat verilog thing
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2021-04-18 17:48:51 -04:00 |
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Noah Boorstin
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6954e6df4c
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buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
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2021-04-17 14:44:32 -04:00 |
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Noah Boorstin
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4f97e9e761
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start to add buildroot testbench
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
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2021-04-16 23:27:29 -04:00 |
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bbracker
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290b3424e5
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-15 21:09:27 -04:00 |
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bbracker
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368c94d4ff
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working GPIO interrupt demo
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2021-04-15 21:09:15 -04:00 |
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Domenico Ottolia
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9f13ee3f31
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Add tests for scause and ucause
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2021-04-15 19:41:25 -04:00 |
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Domenico Ottolia
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531423d7e1
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Add 32 bit privileged tests
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2021-04-15 16:55:39 -04:00 |
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Jarred Allen
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81c02bda55
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Merge branch 'main' into cache
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2021-04-15 13:47:19 -04:00 |
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Thomas Fleming
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3c49fd08f6
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Remove imem from testbenches
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2021-04-14 20:20:34 -04:00 |
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Jarred Allen
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c1e2e58ebe
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Merge branch 'main' into cache
Conflicts:
wally-pipelined/src/cache/dmapped.sv
wally-pipelined/src/cache/line.sv
wally-pipelined/src/ifu/icache.sv
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2021-04-14 18:24:32 -04:00 |
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