David Harris
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231f52c1fd
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fmalza edits to match textbook
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2022-08-01 18:23:39 +00:00 |
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David Harris
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e3b970d3ff
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Partitioned fma into separate files
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2022-08-01 18:07:38 +00:00 |
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David Harris
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d2de84a456
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Added parity and stop bit tests to UART
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2022-07-28 04:35:51 +00:00 |
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David Harris
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da275e3c26
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Increased timeout threshold to avoid timeout building riscof tests on slow machine
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2022-07-27 04:05:21 +00:00 |
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David Harris
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ae4ea00ff0
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fixed testbench merge comflict
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2022-07-26 06:21:46 -07:00 |
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David Harris
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449c80b5f7
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More work toward riscof tests
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2022-07-26 06:19:13 -07:00 |
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David Harris
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094aacdf6f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-25 23:29:08 +00:00 |
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David Harris
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ccf8ccfa24
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Added rv32f tests to RV64gc
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2022-07-25 23:29:05 +00:00 |
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David Harris
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539174f6f6
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Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
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2022-07-25 16:23:10 -07:00 |
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David Harris
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55ab81e37b
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More riscof makefile tuning
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2022-07-25 21:15:56 +00:00 |
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David Harris
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6b172723bd
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Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings
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2022-07-25 20:50:38 +00:00 |
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Ross Thompson
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70032bf8f4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-23 08:41:59 -05:00 |
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Ross Thompson
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5cd6c8069d
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signal name cleanup.
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2022-07-22 23:36:27 -05:00 |
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Ross Thompson
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7d026e02f2
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cache cleanup after removing replay on cpubusy.
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2022-07-22 23:30:25 -05:00 |
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Ross Thompson
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706bc819e1
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cache fsm cleanup after removal of replay.
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2022-07-22 23:25:09 -05:00 |
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Ross Thompson
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0f586c9ed3
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Possible improvement to cache which removes the cpu_busy states.
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2022-07-22 23:20:37 -05:00 |
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Katherine Parry
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bd336f18b3
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merged radix-2 sqrt into divider - doesnt work yet
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2022-07-23 00:41:18 +00:00 |
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slmnemo
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5b71ceac5c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-22 17:13:38 -07:00 |
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slmnemo
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0bfc3fda1b
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Fixed UART FIFO bugs and added FIFO tests
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2022-07-22 17:13:19 -07:00 |
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Daniel Torres
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b726b05d61
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fixed wally rv32e tests, updated regression makefile to new testflow
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2022-07-22 17:09:46 -07:00 |
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Katherine Parry
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ee7932c804
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divider sizes reworked to match book
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2022-07-22 22:02:04 +00:00 |
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Daniel Torres
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d95b266d49
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changes to test.vh for compatability
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2022-07-22 15:00:48 -07:00 |
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Daniel Torres
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2bbfd67082
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added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
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2022-07-22 14:58:55 -07:00 |
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slmnemo
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44c30ec082
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fixed error in tests.vh
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2022-07-22 14:55:55 -07:00 |
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slmnemo
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170601af0b
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Added UART test to peripheral test
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2022-07-22 14:55:34 -07:00 |
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Daniel Torres
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fbe3a1af12
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 13:52:19 -07:00 |
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Daniel Torres
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261b9aa5a1
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commented out embench test that should be commented out
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2022-07-22 13:52:13 -07:00 |
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slmnemo
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49329b3f42
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-22 12:36:06 -07:00 |
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slmnemo
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0d98ff74b4
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Added PLIC test to regression
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2022-07-22 12:35:37 -07:00 |
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Daniel Torres
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5d7171f6f8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 11:16:09 -07:00 |
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Daniel Torres
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526f70e772
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commiting current changes to riscof wally tests
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2022-07-22 11:14:04 -07:00 |
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cturek
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338f44dfc8
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Square root negative exponent handling
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2022-07-22 16:45:19 +00:00 |
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slmnemo
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49565f944c
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Added PLIC and UART tests and new functions to the test library
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2022-07-22 07:10:39 -07:00 |
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David Harris
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07c946bb04
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Reset MSR on read
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2022-07-22 04:29:27 +00:00 |
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Daniel Torres
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f1578936b8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 20:59:01 -07:00 |
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Daniel Torres
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bd918d37ba
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added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
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2022-07-21 20:58:58 -07:00 |
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slmnemo
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99dcff80c9
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-21 20:35:52 -07:00 |
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slmnemo
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bfa500234d
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Fixed UART bug related to parity and MSR/LSR
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2022-07-21 20:35:46 -07:00 |
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cturek
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c170a8d9b6
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Changed testbench to operate on two inputs and one output, changed all test generators, changed srt module to return only one output and take in Mod as a signal to compute integer remainder
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2022-07-22 01:27:08 +00:00 |
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cturek
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abe1ff906e
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Renamed variables, moved output handling to postprocessor, added remainder handling
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2022-07-21 20:45:08 +00:00 |
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Daniel Torres
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a17361870f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 12:50:04 -07:00 |
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Daniel Torres
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6e9b4f4075
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removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
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2022-07-21 12:47:51 -07:00 |
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Katherine Parry
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e330a840b0
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-21 19:38:15 +00:00 |
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Katherine Parry
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270216dd02
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radix-4 division integrated into srt - not tested
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2022-07-21 19:38:06 +00:00 |
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cturek
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ddc237f6bc
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Division working too
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2022-07-21 17:59:10 +00:00 |
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cturek
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9c694b887e
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Updated Radix2 Sqrt to follow new algorithm
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2022-07-21 17:36:21 +00:00 |
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Katherine Parry
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67c99d3d1a
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added input enables and improved forwarding
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2022-07-21 01:20:06 +00:00 |
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Katherine Parry
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e8c9830b88
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turn off 2 word store durring non-fp instructions
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2022-07-20 21:57:23 +00:00 |
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Ross Thompson
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9868e685a4
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Minor cleanup of cache.
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2022-07-19 23:04:23 -05:00 |
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Ross Thompson
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6c8ac7851e
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Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
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2022-07-19 22:42:25 -05:00 |
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