Ross Thompson
79b17c5b55
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
Ross Thompson
7fe70c3cc6
Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.
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1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.
There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop
for each TLB line.
2021-12-23 12:40:22 -06:00
Ross Thompson
8416cae3fe
Fixed Type 5b interaction between dcache and hptw.
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This is a load concurrent with ITLBMiss.
2021-12-20 18:33:31 -06:00
Ross Thompson
beb1988539
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
8feb36b926
Signal renames.
2021-12-19 22:21:03 -06:00
Ross Thompson
dc82d44f9e
Hardware reductions in the lsu.
2021-12-19 22:00:28 -06:00
Ross Thompson
dc95896303
Removed HPTWStall. Not needed as InterlockStall from the LSU provides the equivalent.
2021-12-19 21:36:54 -06:00
Ross Thompson
138da1fefa
Removed lsuArb and placed remaining logic in lsu.sv.
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Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
2021-12-19 21:34:40 -06:00
Ross Thompson
f4d778c2f6
Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm.
2021-12-19 15:10:33 -06:00
Ross Thompson
a445bedcd2
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
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This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
225cd5a114
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
bbd1332353
Merge remote-tracking branch 'origin/tlb_fixes' into main
2021-12-17 14:40:29 -06:00
Ross Thompson
a11597b6bd
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
ee81cfff0c
Possible fix for icache deadlock interaction with hptw.
2021-12-17 14:38:25 -06:00
David Harris
865d5ce0b1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
Ross Thompson
f4c221f20a
Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
2021-11-17 12:47:19 -06:00
David Harris
c9e9cd4a60
more lsu/ifu lint cleanup
2021-10-23 12:10:13 -07:00
David Harris
62a23fe878
lsu/ifu lint cleanup
2021-10-23 11:41:20 -07:00
David Harris
61fdb3d902
random lint cleanup
2021-10-23 11:24:36 -07:00
David Harris
8d9efcbafb
IEU cleanup
2021-10-23 11:13:28 -07:00
David Harris
11b0607e63
Lint cleanup
2021-10-23 09:06:21 -07:00
Ross Thompson
de4ea16d32
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
Ross Thompson
cd58a388e4
fixed issues with dc shell not liking modules with parameters without default values.
2021-10-18 17:24:15 -05:00
Ross Thompson
f6c6cb9ed2
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
kipmacsaigoren
7fde7aae6e
Merging new changes into the old one's I've made in the OKstate servers
2021-10-08 17:47:11 -05:00
Kip Macsai-Goren
f3058f94c6
removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions.
2021-10-08 15:33:18 -07:00
Ross Thompson
44196af61a
Have program which checks for sdc init and issues read, but read done is
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not correctly being read back by the software. The error is in how the
sdc indicates busy.
2021-09-24 15:53:38 -05:00
Ross Thompson
fea439b84d
SDC to ABHLite interface partially done.
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Added SDC to adrdec and uncore.
2021-09-24 10:45:09 -05:00
Kip Macsai-Goren
4de4774a71
more input changes on prioirty thermometer. passes lint
2021-09-17 13:07:21 -04:00
kipmacsaigoren
cc4ad218cb
added new fun ways of putting inputs into the priority thermometer
2021-09-17 12:00:38 -05:00
kipmacsaigoren
97c474327c
changed priority circuits for synthesis and light cleanup
2021-09-15 12:24:24 -05:00
David Harris
12bd351edf
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
James E. Stine
02a1fda650
Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR
2021-09-03 10:26:38 -05:00
Ross Thompson
35e57a7c61
partial dcache reorg.
2021-08-25 12:42:05 -05:00
Ross Thompson
a70d51f4c9
Modified the hptw's simulation error message so that synthesis does not attempt to include this statement.
2021-08-16 10:02:29 -05:00
Ross Thompson
ef55b30e99
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-26 11:55:00 -05:00
Ross Thompson
60177b92a6
Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation.
2021-07-25 23:14:28 -05:00
kipmacsaigoren
f3579032bd
Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's
2021-07-23 11:57:58 -05:00
David Harris
5d2b30e332
Removed LEVELx states from HPTW
2021-07-23 08:11:15 -04:00
Ross Thompson
dac93bb366
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
c69a5dc8a6
fixed issue with tlbflush remaining high during a stalled sfence instruction
2021-07-21 17:43:36 -04:00
Ross Thompson
71375ba655
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:39:07 -05:00
Ross Thompson
313bc5255c
Improved address bus names and usages in the walker, dcache, and tlbs.
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Merge branch 'walkerEnhance' into main
2021-07-21 14:55:09 -05:00
Kip Macsai-Goren
4eaf95de60
Fixed TLB parameterization and valid bit flop to correctly do instr page faults
2021-07-21 14:44:43 -04:00
Kip Macsai-Goren
2614df627e
added changes to priority encoders from synthesis branch (correctly this time I hope)
2021-07-19 15:06:14 -04:00
Ross Thompson
4d53b9002f
Broken.
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Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
David Harris
4f8f52f283
Added FLEN, NE, NF to config and started using these in FMA1
2021-07-18 17:28:25 -04:00
David Harris
8317be5aed
Renamed pagetablewalker to hptw
2021-07-18 04:11:33 -04:00
David Harris
3f7a3b280e
HPTW: Simpliifieid PRegEn
2021-07-18 03:35:38 -04:00
