Ross Thompson
400b5f7632
Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
2022-04-04 09:57:26 -05:00
Ross Thompson
3ebb7f1057
fpga simulation works again.
2022-04-03 17:31:07 -05:00
Kip Macsai-Goren
37c755e6ce
added RV64IA config to have a config without compressed instructions
2022-04-02 18:24:08 +00:00
Ross Thompson
691f1a6b0d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-01 17:18:25 -05:00
Ross Thompson
51dfa16f59
Updated the fpga test bench.
2022-04-01 17:14:47 -05:00
bbracker
9d26bfe71d
expand WALLY-PERIPH test to use SEIP on PLIC context 1
2022-03-31 18:02:06 -07:00
Kip Macsai-Goren
eb337fd3e1
added test config that doesn't use compressed instructions for privileged tests
2022-03-28 19:12:31 +00:00
Skylar Litz
f91fb7a388
add AtemptedInstructionCount signal
2022-03-26 21:28:57 +00:00
Skylar Litz
62a330c290
update to match new filesystem organization
2022-03-26 21:28:32 +00:00
bbracker
d645666fe7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-04 00:06:27 +00:00
bbracker
79ff8d3c80
remove imperas32p tests
2022-03-04 00:06:18 +00:00
David Harris
6431ad4a8b
Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
2022-03-03 15:38:08 +00:00
bbracker
87aad1d953
fix peripheral test and add it to regression
2022-03-02 23:44:39 +00:00
bbracker
e9e827c83e
add CSRs to waveview
2022-03-02 18:31:10 +00:00
bbracker
4fe35aadf2
add rv32a tests to regression
2022-03-02 17:54:55 +00:00
bbracker
b6031bb15f
fix buildroot checkpointing and add it back to regression
2022-03-02 16:00:19 +00:00
bbracker
29179c6787
add LRSC test and add wally64a to regression
2022-03-02 07:09:37 +00:00
bbracker
d2fa5fa645
buildroot graphical sim bugfix
2022-03-01 03:24:23 +00:00
bbracker
a8e8cfb838
switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
2022-03-01 03:11:43 +00:00
bbracker
d8ddda760b
deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
2022-03-01 00:37:46 +00:00
David Harris
dbd73e8cfd
Moved regression work directories to regression/wkdir to reduce clutter
2022-02-27 17:35:09 +00:00
David Harris
5b15e552c6
Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue
2022-02-27 15:12:10 +00:00
David Harris
ff674b695c
Moved Softfloat / TestFloat
2022-02-26 19:17:32 +00:00
Ross Thompson
834b308ed6
Fixed "bug" with wally-pipelined.do
2022-02-22 22:19:25 -06:00
bbracker
202bd2f8f8
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
2022-02-22 03:46:08 +00:00
Ross Thompson
a7b774e453
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
d152733a17
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
Ross Thompson
4cfb601dc8
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
565ca4e4a3
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
460b37b21a
Added additional suppresses to vsim command incase buildroot files are missing.
2022-02-16 17:05:54 -06:00
Skylar Litz
03f23d2aaa
update bugfinder script to new file organization
2022-02-15 22:58:18 +00:00
Ross Thompson
1d7949513d
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
33beaa4593
Updates to linux wave.
2022-02-11 13:28:18 -06:00
Ross Thompson
d9f77d3659
Updated linux wave.
2022-02-11 13:15:42 -06:00
Ross Thompson
1a1629c62f
linux wave cleanup.
2022-02-11 10:48:45 -06:00
Ross Thompson
6d12010d02
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
Ross Thompson
9fb612d4ff
Updated wave files to reflect recent changes.
2022-02-10 17:52:19 -06:00
Ross Thompson
4fd0154d03
Added commented out commands to generate saif file from vsim.
2022-02-09 18:40:45 -06:00
David Harris
c61cd55c5c
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
David Harris
cbef88ec10
Lab 3 file cleanup
2022-02-08 10:26:37 +00:00
David Harris
50b44b4416
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-07 14:43:31 +00:00
David Harris
9b55848ffc
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
2022-02-06 01:22:40 +00:00
bbracker
74ef58e20e
remove rv32e from regression because it is broken; goes with previous commit
2022-02-05 23:05:21 +00:00
David Harris
0f7b8017d1
Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit
2022-02-05 05:35:51 +00:00
David Harris
a9d2386010
Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts
2022-02-05 05:28:40 +00:00
David Harris
66b4834ef5
Modified wally-pipelined-batch.do to handle buildroot
2022-02-05 05:07:07 +00:00
David Harris
72bc64ef28
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
2022-02-05 04:16:18 +00:00
David Harris
2c67f32b97
RV32e tests
2022-02-04 14:30:36 +00:00
David Harris
ef5af9b5fd
renamed configs
2022-02-03 23:36:41 +00:00
