Ross Thompson 6d12010d02 Fixed subtle and infrequenct bug. ... Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.		2022-02-11 10:46:06 -06:00
..
slack-notifier	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wave-dos	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
buildrootBugFinder.py	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
fpga-wave.do	cache cleanup	2022-02-03 15:36:11 +00:00
lint-wally	Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration	2022-02-06 01:22:40 +00:00
linux-wave.do	Fixed subtle and infrequenct bug.	2022-02-11 10:46:06 -06:00
make-tests.sh	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
Makefile	Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the	2022-02-03 08:32:48 -06:00
makefile-memfile	Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the	2022-02-03 08:32:48 -06:00
regression-wally	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
sim-buildroot	Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts	2022-02-05 05:28:40 +00:00
sim-buildroot-batch	Modified wally-pipelined-batch.do to handle buildroot	2022-02-05 05:07:07 +00:00
sim-coremark-batch	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sim-fp64	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sim-fp64-batch	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sim-wally	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
sim-wally-batch	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
wally-coremark.do	Improve wavefile by adding performance counters.	2022-01-12 10:53:29 -06:00
wally-fp64-batch.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-fp64.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-harvard.do	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
wally-pipelined-batch.do	Modified wally-pipelined-batch.do to handle buildroot	2022-02-05 05:07:07 +00:00
wally-pipelined-fpga.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-pipelined.do	Updated wave files to reflect recent changes.	2022-02-10 17:52:19 -06:00
wave-all.do	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
wave-coremark.do	cache cleanup	2022-02-03 15:36:11 +00:00
wave.do	Updated wave files to reflect recent changes.	2022-02-10 17:52:19 -06:00