David Harris
72e83db9fe
removed csrn and all of its outputs because depricated
2022-02-15 19:59:29 +00:00
David Harris
d3034c4f01
Mostly removed N_SUPPORTED
2022-02-15 19:50:44 +00:00
David Harris
f734afb866
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
2022-02-15 19:48:49 +00:00
David Harris
1326ade1a0
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
2022-02-15 19:20:41 +00:00
David Harris
1d5c8a7b98
t push
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
Ross Thompson
1bb4d46ac1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-13 18:21:15 -06:00
Ross Thompson
e852cb8a31
Eliminated more ports in cacheway.
2022-02-13 15:53:46 -06:00
Ross Thompson
1d7949513d
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
a5ad4331ec
More cache cleanup.
2022-02-13 12:38:39 -06:00
David Harris
b360e7b941
Synthesis cleanup
2022-02-12 06:25:12 +00:00
David Harris
a34cbdb7d0
Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0
2022-02-12 05:50:34 +00:00
Ross Thompson
dd944265aa
Formating improvements to cache.
2022-02-11 23:10:58 -06:00
Ross Thompson
bf173b035c
More cache simplifications.
2022-02-11 22:54:05 -06:00
Ross Thompson
16abe90a0d
Reduced seladr to 1 bit as second bit is same as selflush.
2022-02-11 22:41:36 -06:00
Ross Thompson
b11e9eca7b
Reduced complexity of the address selection during flush.
2022-02-11 22:27:27 -06:00
Ross Thompson
1255e82154
Removed redundant signals from cache.
2022-02-11 22:23:47 -06:00
Ross Thompson
52894a7a4f
Cache fsm simplifications.
2022-02-11 15:16:45 -06:00
Ross Thompson
e2e0a4f595
Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
2022-02-11 15:09:00 -06:00
Ross Thompson
0f2ac0cb24
Simplified cache fsm.
2022-02-11 14:54:57 -06:00
Ross Thompson
1c83914662
Fixed bug.
...
It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
Ross Thompson
febd019854
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-11 10:47:21 -06:00
Ross Thompson
6d12010d02
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
David Harris
de5e80696d
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
Ross Thompson
689c32215f
Fixed bugs in ifu spills and missing reset on bus data register.
2022-02-10 18:11:57 -06:00
Ross Thompson
5fd22caed4
Replacement policy cleanup.
2022-02-10 11:42:40 -06:00
Ross Thompson
f716cce832
Replacement policy cleanup.
2022-02-10 11:40:10 -06:00
Ross Thompson
104a9acf81
Cleanup.
2022-02-10 11:27:15 -06:00
Ross Thompson
fdb4f909fc
Cleanup + critical path optimizations.
2022-02-10 11:11:16 -06:00
Ross Thompson
88c7a94aa9
Cache name clarifications.
2022-02-10 10:50:17 -06:00
Ross Thompson
32eee5a06a
More cache cleanup.
2022-02-10 10:43:37 -06:00
Ross Thompson
91f2b5adf5
structural muxes.
2022-02-09 19:36:21 -06:00
Ross Thompson
7ff715f44f
More cache cleanup.
2022-02-09 19:29:15 -06:00
Ross Thompson
754bd41fde
Cleaned up comments.
2022-02-09 19:21:35 -06:00
Ross Thompson
36ab78ef3b
Removed all possilbe paths to PreSelAdr from TrapM.
2022-02-09 19:20:10 -06:00
Ross Thompson
7810a09782
Annotated the final changes required to move sram address off the critial path.
2022-02-08 18:17:31 -06:00
Ross Thompson
30d6514661
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 17:52:15 -06:00
Ross Thompson
4a7ebb3757
Cache cleanup write enables.
2022-02-08 17:52:09 -06:00
Ross Thompson
bdb3794d5e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 15:43:18 -06:00
Ross Thompson
c2907ec0f4
Cleanup IFU.
2022-02-08 14:54:53 -06:00
Ross Thompson
038897f448
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 14:47:15 -06:00
Ross Thompson
4273775a2b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 14:22:19 -06:00
Ross Thompson
e02bc8db67
rv32e works for now. Still need to optimize.
2022-02-08 14:21:55 -06:00
Ross Thompson
f211fe635a
Moved some muxes back into the bp.
2022-02-08 14:17:44 -06:00
David Harris
1479762ae9
RAM simplification
2022-02-08 20:15:23 +00:00
Ross Thompson
aa12d90272
Temporary commit which gets the no branch predictor implementation working.
2022-02-08 14:13:55 -06:00
Ross Thompson
8a2ee22395
Finished merge.
2022-02-08 11:36:24 -06:00
Ross Thompson
e2191e3637
Preparing to make a major change to the cache's write enables.
2022-02-08 09:47:01 -06:00
David Harris
c61cd55c5c
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
Ross Thompson
5c9e23527d
cachefsm cleanup.
2022-02-07 22:09:56 -06:00
