Ross Thompson
9e1f76baa0
Fixed lint issues with SDC.
2021-12-29 20:18:00 -06:00
David Harris
75c0c8ebea
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 00:53:44 +00:00
David Harris
866a5efc43
rv32i regression and linting
2021-12-30 00:53:39 +00:00
Katherine Parry
1d4ff095cf
all FCVT imperas tests pass
2021-12-30 00:19:40 +00:00
Ross Thompson
fd1c4b7313
Added default to busfsm.
2021-12-29 17:53:24 -06:00
Ross Thompson
87b7f80282
Moved lsu interlock fpm to separate module.
2021-12-29 17:40:24 -06:00
Ross Thompson
1955b6e740
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:35:45 -06:00
Ross Thompson
56d86f4dd5
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:12:29 -06:00
Ross Thompson
ac5746c721
Name cleanup in LSU.
2021-12-29 16:34:35 -06:00
Ross Thompson
aa227ce97c
Changed names of lsu address signals.
2021-12-29 15:03:34 -06:00
Ross Thompson
60f0339690
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-29 14:48:16 -06:00
Ross Thompson
e36a037afa
Added more generates around virtual memory and csrs in the lsu.
2021-12-29 14:48:09 -06:00
James E. Stine
2339e3a483
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 13:01:27 -06:00
James E. Stine
2e5b805b0a
Add configuration for IEEE 754 or non IEEE 754 per RISC-V guidelines
...
Katherine/James
2021-12-29 12:59:17 -06:00
Ross Thompson
995cfb1cf3
Cleaned up some names in dcache and lsu.
2021-12-29 11:21:44 -06:00
Ross Thompson
bc6e776609
Converted mux4 to mux3 in dcache.
2021-12-29 10:58:02 -06:00
Ross Thompson
5ebaeb5d90
Simplified the dcache to bus address generation.
2021-12-29 10:46:48 -06:00
Ross Thompson
15f1627a31
Fixed interrupt delay bug by reverting CommittedM changes.
2021-12-28 22:27:12 -06:00
Ross Thompson
29b3285c8e
Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters.
...
Fixed bug with the uncached memory operations. The periph tests still do not pass. They enter into what seems an intentional infinite loop. Then a uart interrupt jumps into an ISR but the ISR returns back to the loop.
2021-12-28 21:28:03 -06:00
Ross Thompson
67a33a80f9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-28 20:22:36 -06:00
David Harris
40e0e6a401
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 00:29:12 +00:00
David Harris
d78b806332
Added performance counting to sumtest and added imperas32/64periph to testbench.
2021-12-29 00:28:51 +00:00
Ross Thompson
d64fe4b1c1
LSU Bus FSM beautification.
2021-12-28 16:53:53 -06:00
Ross Thompson
a966764d88
Removed CommittedM as it is redundant with LSUStall.
2021-12-28 16:14:10 -06:00
Ross Thompson
7044277165
Changed the bus name between dcache and ebu.
2021-12-28 15:57:36 -06:00
Ross Thompson
00ad3a18fb
Reverted changes to subwordread while keeping the new names of the i/o.
2021-12-28 15:57:21 -06:00
Ross Thompson
fe5f016a16
Name changes for states in LSU.
2021-12-28 15:03:24 -06:00
Ross Thompson
c1789932a4
Added generate around virtual memory hardware in LSU.
2021-12-28 15:00:02 -06:00
Ross Thompson
daac21b3bd
Moved generate for lrsc to lsu.
2021-12-28 14:17:18 -06:00
Ross Thompson
b6f4efd458
More cleanup of dcache.
2021-12-28 14:12:18 -06:00
Ross Thompson
22bfc80e62
Additional cleanup of the LSU.
2021-12-28 13:59:07 -06:00
Ross Thompson
b4ab435bff
Major cleanup of the LSU.
2021-12-28 13:10:45 -06:00
Ross Thompson
c2b0e61466
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
Ross Thompson
77e8ba619e
Minor dcache cleanup.
2021-12-28 11:29:16 -06:00
Ross Thompson
d6960da90e
Moved all bus logic outside the dcache. Still needs cleanup.
2021-12-28 11:18:47 -06:00
Ross Thompson
44b63fc0ba
First cut at moving the dcache bus interface into the LSU.
...
Regression test does not run and there is a lot of cleanup to do.
2021-12-27 18:12:59 -06:00
Ross Thompson
3e7ec1e9a2
Moved dcache fetch logic outside the dcache except for the fsm.
2021-12-27 16:45:49 -06:00
Ross Thompson
3ee29785a4
Partial commit.
...
Moved AMO, SWW, and SWR outside the dcache.
Step 1 of separate the fetching logic from the caches.
2021-12-27 15:56:18 -06:00
David Harris
52469db9ff
Added D and F tests to regression
2021-12-27 04:35:34 +00:00
David Harris
69243f41ad
Fixed imperas C tests
2021-12-26 04:45:06 +00:00
David Harris
a7cfda8e52
Incorporated new Imperas tests. f and d tests are failing and c tests are hanging.
2021-12-26 04:36:53 +00:00
David Harris
e97e512da9
Started FIR test code and started incorporating Imperas tests
2021-12-25 22:39:51 +00:00
David Harris
35e31006a9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-25 06:37:30 -08:00
David Harris
37b091e5da
Checked in Chapter 2 C and assembly examples
2021-12-25 06:35:36 -08:00
Ross Thompson
ae0cc085b4
Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.
...
1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.
There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop
for each TLB line.
2021-12-23 12:40:22 -06:00
Ross Thompson
42ad710213
linux-wave.do changes.
2021-12-21 22:37:55 -06:00
Ross Thompson
50e4463a7f
It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.
2021-12-21 15:59:56 -06:00
Ross Thompson
4ae15bf5e4
Fixed bug where the wrong address is read into the icache memory.
2021-12-21 15:16:00 -06:00
Ross Thompson
0a7dc96052
Fixed complex bug where FENCE is instruction class miss predicted as a taken branch.
2021-12-21 11:29:28 -06:00
Ross Thompson
b0507b96b0
Identified bug in the IFU which selects PCNextF when InvalidateICacheM is true. If the ID is invalid PCNextF should NOT be PCE.
2021-12-20 23:45:55 -06:00
Ross Thompson
a02ac78907
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 23:27:46 -06:00
Ross Thompson
0bc3bcf406
Fixed bug on icache spill. if the cpu stalled on the completion it was possible to use the wrong address for the sram read. Also miss spill hit always selected the wrong address.
2021-12-20 23:27:37 -06:00
David Harris
0c57b61ace
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-20 21:09:20 -08:00
David Harris
001c39d8eb
Fixing paths in wally-setup.sh
2021-12-20 21:08:34 -08:00
Ross Thompson
47638cdccf
Looks like rdtime was accidentally replaced with rrame from a find and replace.
2021-12-20 21:26:38 -06:00
Ross Thompson
d830721a11
Fixed Type 5b interaction between dcache and hptw.
...
This is a load concurrent with ITLBMiss.
2021-12-20 18:33:31 -06:00
Ross Thompson
6aff6b0fa3
Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM.
2021-12-20 10:03:56 -06:00
Ross Thompson
53736096a6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
b261b18aa8
More signal name cleanup in LSU.
2021-12-19 22:47:48 -06:00
Ross Thompson
533c2f3556
Remove verbosity from lsu state machine.
2021-12-19 22:41:34 -06:00
Ross Thompson
82dd41a0fd
Rename of SelPTW to SelHPTW.
2021-12-19 22:24:07 -06:00
Ross Thompson
9c2fc30507
Signal renames.
2021-12-19 22:21:03 -06:00
Ross Thompson
2f5de7eb82
Hardware reductions in the lsu.
2021-12-19 22:00:28 -06:00
Ross Thompson
035ce99938
Removed HPTWStall. Not needed as InterlockStall from the LSU provides the equivalent.
2021-12-19 21:36:54 -06:00
Ross Thompson
30770db4ac
Removed lsuArb and placed remaining logic in lsu.sv.
...
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
2021-12-19 21:34:40 -06:00
Ross Thompson
db76878581
Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card.
...
mv qemu patches to tests directory.
2021-12-19 20:11:32 -06:00
David Harris
193885c958
Moved generate of conditional units to hart
2021-12-19 17:03:57 -08:00
David Harris
1196e5c191
Moved generate statements for optional units into wallypipelinedhart
2021-12-19 16:53:41 -08:00
Ross Thompson
7b2f5440a5
Changes to buildroot to support MemAdrM to IEUAdrM name changes.
2021-12-19 18:24:40 -06:00
Ross Thompson
aeb8c94df1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-19 18:16:49 -06:00
Ross Thompson
cef4b6399d
Switched to using an always block for lsu stall logic. This avoids the problematic x propagation.
2021-12-19 18:16:08 -06:00
Ross Thompson
814bcec7b7
Implemented what I think is the last required change for the lsu state machine.
2021-12-19 17:57:12 -06:00
Ross Thompson
54fd8678b0
Created hack to get around imperas64mmu unknown (value = x) bug.
2021-12-19 17:53:13 -06:00
Ross Thompson
13f0e9bafa
Fixed bug where icache did not replay PCF on itlb miss.
2021-12-19 17:01:13 -06:00
Ross Thompson
04d0b85f96
Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
2021-12-19 16:12:31 -06:00
David Harris
5e1c3e322b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-19 13:53:53 -08:00
David Harris
691c1c0dd0
ALUControl cleanup
2021-12-19 13:53:45 -08:00
Katherine Parry
ece9e9df84
fixed some small errors in FMA
2021-12-19 13:51:46 -08:00
Ross Thompson
202203904c
Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm.
2021-12-19 15:10:33 -06:00
Ross Thompson
9adcf86a40
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
...
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
0257c08641
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
620f4a58d4
Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states.
2021-12-19 13:55:57 -06:00
Ross Thompson
fdf493bd47
minro change. comments about needed changes in dcache.
2021-12-19 13:53:02 -06:00
David Harris
c04c56dae1
Renamed zero to eq in flag generation
2021-12-19 11:49:15 -08:00
David Harris
e5d2d7a3fd
Controller fix
2021-12-18 22:08:23 -08:00
David Harris
8a597390e0
Renamed RD1D to R1D, etc.
2021-12-18 21:26:00 -08:00
David Harris
7fb4213751
Simplified shifter right input
2021-12-18 10:25:40 -08:00
Ross Thompson
f601b3ae53
Merge branch 'tlb_fixes' into main
2021-12-18 12:24:17 -06:00
David Harris
d97d34ee32
Simplified Shifter Right input
2021-12-18 10:21:17 -08:00
David Harris
852c521328
Shared ALU mux input for shifts
2021-12-18 10:08:52 -08:00
David Harris
a7d7f852a6
Factored out common parts of shifter
2021-12-18 10:01:12 -08:00
David Harris
7868c0da55
Cleaning shifter
2021-12-18 09:43:09 -08:00
David Harris
b453454b24
Moved W64 truncation after result mux
2021-12-18 09:27:25 -08:00
David Harris
2a5a7eff82
Forwarding logic factoring
2021-12-18 05:40:38 -08:00
David Harris
1212e21eba
Simplified FWriteInt interfaces by merging into RegWrite
2021-12-18 05:36:32 -08:00
David Harris
da1df17fbb
Do File cleanups
2021-12-17 17:45:26 -08:00
Ross Thompson
2f86e84843
Merge remote-tracking branch 'origin/tlb_fixes' into main
2021-12-17 14:40:29 -06:00
Ross Thompson
79ec4161b6
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
5264577dcf
Possible fix for icache deadlock interaction with hptw.
2021-12-17 14:38:25 -06:00
David Harris
3a9071e509
Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
2021-12-15 12:10:45 -08:00
