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Changed the bus name between dcache and ebu.

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This commit is contained in:
Ross Thompson 2021-12-28 15:57:36 -06:00
parent 00ad3a18fb
commit 7044277165
4 changed files with 54 additions and 54 deletions
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2
wally-pipelined/regression/wave.do
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@ -186,7 +186,7 @@ add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/LsuBusSize
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA

28
wally-pipelined/src/ebu/ahblite.sv
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@ -45,13 +45,13 @@ module ahblite (
output logic [`XLEN-1:0] InstrRData,
output logic InstrAckF,
// Signals from Data Cache
input logic [`PA_BITS-1:0] DCtoAHBPAdrM,
input logic DCtoAHBReadM,
input logic DCtoAHBWriteM,
input logic [`XLEN-1:0] DCtoAHBWriteData,
output logic [`XLEN-1:0] DCfromAHBReadData,
input logic [1:0] MemSizeM, // *** remove
output logic DCfromAHBAck,
input logic [`PA_BITS-1:0] LsuBusAdr,
input logic LsuBusRead,
input logic LsuBusWrite,
input logic [`XLEN-1:0] LsuBusHWDATA,
output logic [`XLEN-1:0] LsuBusHRDATA,
input logic [2:0] LsuBusSize,
output logic LsuBusAck,
// AHB-Lite external signals
(* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA,
(* mark_debug = "true" *) input logic HREADY, HRESP,
@ -98,8 +98,8 @@ module ahblite (
// interface that might be used in place of the ahblite.
always_comb
case (BusState)
IDLE: if (DCtoAHBReadM) NextBusState = MEMREAD; // Memory has priority over instructions
else if (DCtoAHBWriteM)NextBusState = MEMWRITE;
IDLE: if (LsuBusRead) NextBusState = MEMREAD; // Memory has priority over instructions
else if (LsuBusWrite)NextBusState = MEMWRITE;
else if (InstrReadF) NextBusState = INSTRREAD;
else NextBusState = IDLE;
MEMREAD: if (~HREADY) NextBusState = MEMREAD;
@ -116,17 +116,17 @@ module ahblite (
// bus outputs
assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE);
assign #1 AccessAddress = (GrantData) ? DCtoAHBPAdrM[31:0] : InstrPAdrF[31:0];
assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : InstrPAdrF[31:0];
assign #1 HADDR = AccessAddress;
assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
assign HSIZE = (GrantData) ? {1'b0, MemSizeM} : ISize;
assign HSIZE = (GrantData) ? {1'b0, LsuBusSize[1:0]} : ISize;
assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH
assign HPROT = 4'b0011; // not used; see Section 3.7
assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
assign HMASTLOCK = 0; // no locking supported
assign HWRITE = NextBusState == MEMWRITE;
// delay write data by one cycle for
flop #(`XLEN) wdreg(HCLK, DCtoAHBWriteData, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
flop #(`XLEN) wdreg(HCLK, LsuBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
// delay signals for subword writes
flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD);
flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
@ -137,8 +137,8 @@ module ahblite (
assign InstrRData = HRDATA;
assign DCfromAHBReadData = HRDATA;
assign LsuBusHRDATA = HRDATA;
assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
assign DCfromAHBAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE);
assign LsuBusAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE);
endmodule

52
wally-pipelined/src/lsu/lsu.sv
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@ -63,13 +63,13 @@ module lsu
output logic StoreMisalignedFaultM, StoreAccessFaultM,
// connect to ahb
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] DCtoAHBPAdrM,
output logic DCtoAHBReadM,
output logic DCtoAHBWriteM,
input logic DCfromAHBAck,
(* mark_debug = "true" *) input logic [`XLEN-1:0] DCfromAHBReadData,
output logic [`XLEN-1:0] DCtoAHBWriteData,
output logic [2:0] DCtoAHBSizeM,
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LsuBusAdr,
output logic LsuBusRead,
output logic LsuBusWrite,
input logic LsuBusAck,
(* mark_debug = "true" *) input logic [`XLEN-1:0] LsuBusHRDATA,
output logic [`XLEN-1:0] LsuBusHWDATA,
output logic [2:0] LsuBusSize,
// mmu management
@ -410,11 +410,11 @@ module lsu
.HWDATAIN(FinalAMOWriteDataM),
.HWDATA(FinalWriteDataM));
assign DCtoAHBWriteData = CacheableM | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM;
assign LsuBusHWDATA = CacheableM | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM;
generate
if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b010 : LsuFunct3M;
else assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b011 : LsuFunct3M;
if (`XLEN == 32) assign LsuBusSize = CacheableM | SelFlush ? 3'b010 : LsuFunct3M;
else assign LsuBusSize = CacheableM | SelFlush ? 3'b011 : LsuFunct3M;
endgenerate;
// Bus Side logic
@ -426,8 +426,8 @@ module lsu
generate
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
flopen #(`XLEN) fb(.clk(clk),
.en(DCfromAHBAck & DCtoAHBReadM & (index == FetchCount)),
.d(DCfromAHBReadData),
.en(LsuBusAck & LsuBusRead & (index == FetchCount)),
.d(LsuBusHRDATA),
.q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
end
endgenerate
@ -438,12 +438,12 @@ module lsu
assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM};
assign DCtoAHBPAdrM = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM;
assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM;
assign DC_HWDATA_FIXNAME = ReadDataBlockSetsM[FetchCount];
assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
assign CntEn = PreCntEn & DCfromAHBAck;
assign CntEn = PreCntEn & LsuBusAck;
flopenr #(LOGWPL)
FetchCountReg(.clk(clk),
@ -473,8 +473,8 @@ module lsu
CntReset = 1'b0;
BusStall = 1'b0;
PreCntEn = 1'b0;
DCtoAHBWriteM = 1'b0;
DCtoAHBReadM = 1'b0;
LsuBusWrite = 1'b0;
LsuBusRead = 1'b0;
CommittedMfromBus = 1'b0;
BUSACK = 1'b0;
SelUncached = 1'b0;
@ -489,14 +489,14 @@ module lsu
BusNextState = STATE_BUS_UNCACHED_WRITE;
CntReset = 1'b1;
BusStall = 1'b1;
DCtoAHBWriteM = 1'b1;
LsuBusWrite = 1'b1;
end
// uncached read
else if(DCRWM[1] & ~CacheableM) begin
BusNextState = STATE_BUS_UNCACHED_READ;
CntReset = 1'b1;
BusStall = 1'b1;
DCtoAHBReadM = 1'b1;
LsuBusRead = 1'b1;
end
// D$ Fetch Line
else if(DCFetchLine) begin
@ -514,9 +514,9 @@ module lsu
STATE_BUS_UNCACHED_WRITE : begin
BusStall = 1'b1;
DCtoAHBWriteM = 1'b1;
LsuBusWrite = 1'b1;
CommittedMfromBus = 1'b1;
if(DCfromAHBAck) begin
if(LsuBusAck) begin
BusNextState = STATE_BUS_UNCACHED_WRITE_DONE;
end else begin
BusNextState = STATE_BUS_UNCACHED_WRITE;
@ -525,9 +525,9 @@ module lsu
STATE_BUS_UNCACHED_READ: begin
BusStall = 1'b1;
DCtoAHBReadM = 1'b1;
LsuBusRead = 1'b1;
CommittedMfromBus = 1'b1;
if(DCfromAHBAck) begin
if(LsuBusAck) begin
BusNextState = STATE_BUS_UNCACHED_READ_DONE;
end else begin
BusNextState = STATE_BUS_UNCACHED_READ;
@ -547,10 +547,10 @@ module lsu
STATE_BUS_FETCH: begin
BusStall = 1'b1;
PreCntEn = 1'b1;
DCtoAHBReadM = 1'b1;
LsuBusRead = 1'b1;
CommittedMfromBus = 1'b1;
if (FetchCountFlag & DCfromAHBAck) begin
if (FetchCountFlag & LsuBusAck) begin
BusNextState = STATE_BUS_READY;
BUSACK = 1'b1;
end else begin
@ -561,9 +561,9 @@ module lsu
STATE_BUS_WRITE: begin
BusStall = 1'b1;
PreCntEn = 1'b1;
DCtoAHBWriteM = 1'b1;
LsuBusWrite = 1'b1;
CommittedMfromBus = 1'b1;
if(FetchCountFlag & DCfromAHBAck) begin
if(FetchCountFlag & LsuBusAck) begin
BusNextState = STATE_BUS_READY;
BUSACK = 1'b1;
end else begin

26
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -134,12 +134,12 @@ module wallypipelinedhart (
logic InstrAckF;
// AHB LSU interface
logic [`PA_BITS-1:0] DCtoAHBPAdrM;
logic DCtoAHBReadM;
logic DCtoAHBWriteM;
logic DCfromAHBAck;
logic [`XLEN-1:0] DCfromAHBReadData;
logic [`XLEN-1:0] DCtoAHBWriteData;
logic [`PA_BITS-1:0] LsuBusAdr;
logic LsuBusRead;
logic LsuBusWrite;
logic LsuBusAck;
logic [`XLEN-1:0] LsuBusHRDATA;
logic [`XLEN-1:0] LsuBusHWDATA;
logic BPPredWrongE;
logic BPPredDirWrongM;
@ -148,7 +148,7 @@ module wallypipelinedhart (
logic BPPredClassNonCFIWrongM;
logic [4:0] InstrClassM;
logic InstrAccessFaultF;
logic [2:0] DCtoAHBSizeM;
logic [2:0] LsuBusSize;
logic ExceptionM;
logic PendingInterruptM;
@ -246,8 +246,8 @@ module wallypipelinedhart (
.IEUAdrE, .IEUAdrM, .WriteDataM,
.ReadDataM, .FlushDCacheM,
// connected to ahb (all stay the same)
.DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck,
.DCfromAHBReadData, .DCtoAHBWriteData, .DCtoAHBSizeM,
.LsuBusAdr, .LsuBusRead, .LsuBusWrite, .LsuBusAck,
.LsuBusHRDATA, .LsuBusHWDATA, .LsuBusSize,
// connect to csr or privilege and stay the same.
.PrivilegeModeW, // connects to csr
@ -280,10 +280,10 @@ module wallypipelinedhart (
.InstrPAdrF, // *** rename these to match block diagram
.InstrReadF, .InstrRData, .InstrAckF,
// Signals from Data Cache
.DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCtoAHBWriteData,
.DCfromAHBReadData,
.MemSizeM(DCtoAHBSizeM[1:0]), // *** remove
.DCfromAHBAck,
.LsuBusAdr, .LsuBusRead, .LsuBusWrite, .LsuBusHWDATA,
.LsuBusHRDATA,
.LsuBusSize,
.LsuBusAck,
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,
.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST,