Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
+Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86

wally-pipelined/config/buildroot/wally-config.vh

@@ -36,6 +36,9 @@
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
 
+// IEEE 754 compliance
+`define IEEE754 0
+
 `define MISA (32'h0014112D)
 `define ZICSR_SUPPORTED 1
 `define ZIFENCEI_SUPPORTED 1

wally-pipelined/config/coremark/wally-config.vh

@@ -35,6 +35,9 @@
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
 
+// IEEE 754 compliance
+`define IEEE754 0
+
 //`define MISA (32'h00000104)
 `define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12)
 `define ZICSR_SUPPORTED 1

wally-pipelined/config/coremark_bare/wally-config.vh

@@ -35,6 +35,9 @@
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
 
+// IEEE 754 compliance
+`define IEEE754 0
+
 //`define MISA (32'h00000104)
 //`define MISA (32'h00001104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0)
 `define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)

wally-pipelined/config/fpga/wally-config.vh

@@ -37,6 +37,9 @@
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
 
+// IEEE 754 compliance
+`define IEEE754 0
+
 `define MISA (32'h0014112D)
 `define ZICSR_SUPPORTED 1
 `define ZIFENCEI_SUPPORTED 1

wally-pipelined/config/rv32gc/wally-config.vh

@@ -36,6 +36,9 @@
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 32
 
+// IEEE 754 compliance
+`define IEEE754 0
+
 `define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5)
 `define ZICSR_SUPPORTED 1
 `define ZIFENCEI_SUPPORTED 1

wally-pipelined/config/rv32ic/wally-config.vh

@@ -36,6 +36,9 @@
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 32
 
+// IEEE 754 compliance
+`define IEEE754 0
+
 `define MISA (32'h00000104)
 `define ZICSR_SUPPORTED 1
 `define ZIFENCEI_SUPPORTED 1

wally-pipelined/config/rv64BP/wally-config.vh

@@ -37,6 +37,9 @@
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
 
+// IEEE 754 compliance
+`define IEEE754 0
+
 //`define MISA (32'h00000105)
 `define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 `define ZICSR_SUPPORTED 1

wally-pipelined/config/rv64gc/wally-config.vh

@@ -36,6 +36,9 @@
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
 
+// IEEE 754 compliance
+`define IEEE754 0
+
 // MISA RISC-V configuration per specification
 `define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
 `define ZICSR_SUPPORTED 1

wally-pipelined/config/rv64ic/wally-config.vh

@@ -36,6 +36,9 @@
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
 
+// IEEE 754 compliance
+`define IEEE754 0
+
 // MISA RISC-V configuration per specification
 `define MISA (32'h00000104)
 `define ZICSR_SUPPORTED 1