mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
This commit is contained in:
Ross Thompson
parent
202203904c
commit
04d0b85f96
@ -103,15 +103,15 @@ add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -group {instruction pipeline} /testbench/InstrW
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
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add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
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@ -168,86 +168,86 @@ add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
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add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/WayHit
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/VictimWay
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/SelAdr
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/RAdr
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/FinalInstrRawF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
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add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
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add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/WayHit
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
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add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/VictimWay
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
|
||||
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SelAdr
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/RAdr
|
||||
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/FinalInstrRawF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
|
||||
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
|
||||
add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
|
||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
|
||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
|
||||
@ -272,7 +272,6 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/hart/hzu/LSUStall
|
||||
add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
|
||||
@ -341,10 +340,10 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
||||
@ -501,8 +500,13 @@ add wave -noupdate /testbench/dut/hart/lsu/CurrState
|
||||
add wave -noupdate /testbench/dut/hart/lsu/InterlockStall
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/PCNextF
|
||||
add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF
|
||||
add wave -noupdate /testbench/dut/hart/lsu/WalkerInstrPageFaultF
|
||||
add wave -noupdate /testbench/dut/hart/lsu/WalkerPageFaultM
|
||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/RAdr
|
||||
add wave -noupdate /testbench/dut/hart/lsu/dcache/SelAdrM
|
||||
add wave -noupdate /testbench/dut/hart/lsu/SelReplayCPURequest
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 6} {24475 ns} 1} {{Cursor 2} {22501 ns} 1} {{Cursor 3} {23208 ns} 0}
|
||||
WaveRestoreCursors {{Cursor 6} {24475 ns} 1} {{Cursor 2} {22501 ns} 1} {{Cursor 3} {3615 ns} 0}
|
||||
quietly wave cursor active 3
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 297
|
||||
@ -518,4 +522,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {23041 ns} {23377 ns}
|
||||
WaveRestoreZoom {3453 ns} {3729 ns}
|
||||
|
||||
22
wally-pipelined/src/cache/dcache.sv
vendored
22
wally-pipelined/src/cache/dcache.sv
vendored
@ -36,7 +36,7 @@ module dcache
|
||||
input logic [6:0] Funct7M,
|
||||
input logic [1:0] AtomicM,
|
||||
input logic FlushDCacheM,
|
||||
input logic [11:0] IEUAdrE, // virtual address, but we only use the lower 12 bits.
|
||||
input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits.
|
||||
input logic [`PA_BITS-1:0] MemPAdrM, // physical address
|
||||
input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM.
|
||||
|
||||
@ -50,15 +50,9 @@ module dcache
|
||||
// inputs from TLB and PMA/P
|
||||
input logic ExceptionM,
|
||||
input logic PendingInterruptM,
|
||||
input logic DTLBMissM,
|
||||
input logic ITLBMissF,
|
||||
input logic CacheableM,
|
||||
input logic DTLBWriteM,
|
||||
input logic ITLBWriteF,
|
||||
input logic WalkerInstrPageFaultF,
|
||||
// from ptw
|
||||
input logic SelPTW,
|
||||
input logic WalkerPageFaultM,
|
||||
input logic IgnoreRequest,
|
||||
output logic MemAfterIWalkDone,
|
||||
// ahb side
|
||||
(* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
|
||||
@ -147,8 +141,8 @@ module dcache
|
||||
// Read Path CPU (IEU) side
|
||||
|
||||
mux4 #(INDEXLEN)
|
||||
AdrSelMux(.d0(IEUAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), // *** REMOVE
|
||||
.d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
//.d2(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d3(FlushAdr),
|
||||
@ -354,14 +348,8 @@ module dcache
|
||||
.ExceptionM,
|
||||
.PendingInterruptM,
|
||||
.StallWtoDCache,
|
||||
.DTLBMissM,
|
||||
.ITLBMissF,
|
||||
.CacheableM,
|
||||
.DTLBWriteM,
|
||||
.ITLBWriteF,
|
||||
.WalkerInstrPageFaultF,
|
||||
.SelPTW,
|
||||
.WalkerPageFaultM,
|
||||
.IgnoreRequest,
|
||||
.AHBAck, // from ahb
|
||||
.CacheHit,
|
||||
.FetchCountFlag,
|
||||
|
||||
437
wally-pipelined/src/cache/dcachefsm.sv
vendored
437
wally-pipelined/src/cache/dcachefsm.sv
vendored
@ -36,16 +36,9 @@ module dcachefsm
|
||||
input logic ExceptionM,
|
||||
input logic PendingInterruptM,
|
||||
input logic StallWtoDCache,
|
||||
// mmu inputs
|
||||
input logic DTLBMissM,
|
||||
input logic ITLBMissF,
|
||||
input logic CacheableM,
|
||||
input logic DTLBWriteM,
|
||||
input logic ITLBWriteF,
|
||||
input logic WalkerInstrPageFaultF,
|
||||
// hptw inputs
|
||||
input logic SelPTW,
|
||||
input logic WalkerPageFaultM,
|
||||
input logic IgnoreRequest,
|
||||
// Bus inputs
|
||||
input logic AHBAck, // from ahb
|
||||
// dcache internals
|
||||
@ -101,36 +94,11 @@ module dcachefsm
|
||||
STATE_MISS_READ_WORD_DELAY,
|
||||
STATE_MISS_WRITE_WORD,
|
||||
|
||||
STATE_PTW_READY,
|
||||
STATE_PTW_READ_MISS_FETCH_WDV,
|
||||
STATE_PTW_READ_MISS_FETCH_DONE,
|
||||
STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK,
|
||||
STATE_PTW_READ_MISS_EVICT_DIRTY,
|
||||
STATE_PTW_READ_MISS_READ_WORD,
|
||||
STATE_PTW_READ_MISS_READ_WORD_DELAY,
|
||||
STATE_PTW_ACCESS_AFTER_WALK, // dead state remove
|
||||
|
||||
STATE_UNCACHED_WRITE,
|
||||
STATE_UNCACHED_WRITE_DONE,
|
||||
STATE_UNCACHED_READ,
|
||||
STATE_UNCACHED_READ_DONE,
|
||||
|
||||
STATE_PTW_FAULT_READY,
|
||||
STATE_PTW_FAULT_CPU_BUSY,
|
||||
STATE_PTW_FAULT_MISS_FETCH_WDV,
|
||||
STATE_PTW_FAULT_MISS_FETCH_DONE,
|
||||
STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK,
|
||||
STATE_PTW_FAULT_MISS_READ_WORD,
|
||||
STATE_PTW_FAULT_MISS_READ_WORD_DELAY,
|
||||
STATE_PTW_FAULT_MISS_WRITE_WORD,
|
||||
STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY,
|
||||
STATE_PTW_FAULT_MISS_EVICT_DIRTY,
|
||||
|
||||
STATE_PTW_FAULT_UNCACHED_WRITE,
|
||||
STATE_PTW_FAULT_UNCACHED_WRITE_DONE,
|
||||
STATE_PTW_FAULT_UNCACHED_READ,
|
||||
STATE_PTW_FAULT_UNCACHED_READ_DONE,
|
||||
|
||||
STATE_CPU_BUSY,
|
||||
STATE_CPU_BUSY_FINISH_AMO,
|
||||
|
||||
@ -191,18 +159,16 @@ module dcachefsm
|
||||
LRUWriteEn = 1'b0;
|
||||
CommittedM = 1'b0;
|
||||
|
||||
|
||||
// TLB Miss
|
||||
if(((AnyCPUReqM & DTLBMissM) | ITLBMissF) & ~(ExceptionM | PendingInterruptM)) begin
|
||||
if(IgnoreRequest) begin
|
||||
// the LSU arbiter has not yet selected the PTW.
|
||||
// The CPU needs to be stalled until that happens.
|
||||
// If we set DCacheStall for 1 cycle before going to
|
||||
// PTW ready the CPU will stall.
|
||||
// The page table walker asserts it's control 1 cycle
|
||||
// after the TLBs miss.
|
||||
CommittedM = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
NextState = STATE_PTW_READY;
|
||||
// CommittedM = 1'b1; ??? *** Not Sure yet.
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
|
||||
// Flush dcache to next level of memory
|
||||
@ -215,7 +181,7 @@ module dcachefsm
|
||||
end
|
||||
|
||||
// amo hit
|
||||
else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
|
||||
else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
|
||||
SelAdrM = 2'b10;
|
||||
DCacheStall = 1'b0;
|
||||
|
||||
@ -231,7 +197,7 @@ module dcachefsm
|
||||
end
|
||||
end
|
||||
// read hit valid cached
|
||||
else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
|
||||
else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
|
||||
DCacheStall = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
|
||||
@ -244,7 +210,7 @@ module dcachefsm
|
||||
end
|
||||
end
|
||||
// write hit valid cached
|
||||
else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
|
||||
else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
|
||||
SelAdrM = 2'b10;
|
||||
DCacheStall = 1'b0;
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
@ -260,27 +226,27 @@ module dcachefsm
|
||||
end
|
||||
end
|
||||
// read or write miss valid cached
|
||||
else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
|
||||
else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit) begin
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
CntReset = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
end
|
||||
// uncached write
|
||||
else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
|
||||
else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM)) begin
|
||||
NextState = STATE_UNCACHED_WRITE;
|
||||
CntReset = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
AHBWrite = 1'b1;
|
||||
end
|
||||
// uncached read
|
||||
else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
|
||||
else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM)) begin
|
||||
NextState = STATE_UNCACHED_READ;
|
||||
CntReset = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
AHBRead = 1'b1;
|
||||
end
|
||||
// fault
|
||||
else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
|
||||
else if(AnyCPUReqM & (ExceptionM | PendingInterruptM)) begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
else NextState = STATE_READY;
|
||||
@ -394,144 +360,7 @@ module dcachefsm
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_READY: begin
|
||||
// now all output connect to PTW instead of CPU.
|
||||
CommittedM = 1'b1;
|
||||
SelAdrM = 2'b00;
|
||||
DCacheStall = 1'b0;
|
||||
LRUWriteEn = 1'b0;
|
||||
CntReset = 1'b0;
|
||||
|
||||
// In this branch we remove stall and go back to ready. There is no request for memory from the
|
||||
// datapath or the walker had a fault.
|
||||
// types 3b, 4a, 4b, and 7c.
|
||||
if ((DTLBMissM & WalkerPageFaultM) | // 3b or 7c (can have either itlb miss or not)
|
||||
(ITLBMissF & (WalkerInstrPageFaultF | ITLBWriteF) & ~AnyCPUReqM & ~DTLBMissM) | // 4a and 4b
|
||||
(DTLBMissM & ITLBMissF & WalkerPageFaultM)) begin // 7c *** BUG redundant with first condiction.
|
||||
NextState = STATE_READY;
|
||||
DCacheStall = 1'b0;
|
||||
end
|
||||
// in this branch we go back to ready, but there is a memory operation from
|
||||
// the datapath so we MUST stall and replay the operation.
|
||||
// types 3a and 5a
|
||||
else if ((DTLBMissM & DTLBWriteM) | // 3a
|
||||
(ITLBMissF & ITLBWriteF & AnyCPUReqM)) begin // 5a
|
||||
NextState = STATE_READY;
|
||||
DCacheStall = 1'b1;
|
||||
SelAdrM = 2'b01;
|
||||
end
|
||||
|
||||
// like 5a we want to stall and go to the ready state, but we also have to save
|
||||
// the WalkerInstrPageFaultF so it is held until the end of the memory operation
|
||||
// from the datapath.
|
||||
// types 5b
|
||||
else if (ITLBMissF & WalkerInstrPageFaultF & AnyCPUReqM) begin // 5b
|
||||
NextState = STATE_PTW_FAULT_READY;
|
||||
DCacheStall = 1'b1;
|
||||
SelAdrM = 2'b01;
|
||||
end
|
||||
|
||||
// in this branch we stay in ptw_ready because we are doing an itlb walk
|
||||
// after a dtlb walk.
|
||||
// types 7a and 7b.
|
||||
else if (DTLBMissM & DTLBWriteM & ITLBMissF)begin
|
||||
NextState = STATE_PTW_READY;
|
||||
DCacheStall = 1'b0;
|
||||
|
||||
// read hit valid cached
|
||||
end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin
|
||||
NextState = STATE_PTW_READY;
|
||||
DCacheStall = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
end
|
||||
|
||||
// read miss valid cached
|
||||
else if(SelPTW & MemRWM[1] & CacheableM & ~ExceptionM & ~CacheHit) begin
|
||||
NextState = STATE_PTW_READ_MISS_FETCH_WDV;
|
||||
CntReset = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
end
|
||||
|
||||
else begin
|
||||
NextState = STATE_PTW_READY;
|
||||
DCacheStall = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_READ_MISS_FETCH_WDV: begin
|
||||
DCacheStall = 1'b1;
|
||||
PreCntEn = 1'b1;
|
||||
AHBRead = 1'b1;
|
||||
SelAdrM = 2'b10;
|
||||
CommittedM = 1'b1;
|
||||
|
||||
if(FetchCountFlag & AHBAck) begin
|
||||
NextState = STATE_PTW_READ_MISS_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_PTW_READ_MISS_FETCH_WDV;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_READ_MISS_FETCH_DONE: begin
|
||||
DCacheStall = 1'b1;
|
||||
SelAdrM = 2'b10;
|
||||
CntReset = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
CntReset = 1'b1;
|
||||
if(VictimDirty) begin
|
||||
NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
|
||||
end else begin
|
||||
NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_READ_MISS_EVICT_DIRTY: begin
|
||||
DCacheStall = 1'b1;
|
||||
PreCntEn = 1'b1;
|
||||
AHBWrite = 1'b1;
|
||||
SelAdrM = 2'b10;
|
||||
CommittedM = 1'b1;
|
||||
SelEvict = 1'b1;
|
||||
if(FetchCountFlag & AHBAck) begin
|
||||
NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
|
||||
end else begin
|
||||
NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK: begin
|
||||
SRAMBlockWriteEnableM = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
NextState = STATE_PTW_READ_MISS_READ_WORD;
|
||||
SelAdrM = 2'b10;
|
||||
SetValid = 1'b1;
|
||||
ClearDirty = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
//LRUWriteEn = 1'b1;
|
||||
end
|
||||
|
||||
STATE_PTW_READ_MISS_READ_WORD: begin
|
||||
SelAdrM = 2'b10;
|
||||
DCacheStall = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
NextState = STATE_PTW_READ_MISS_READ_WORD_DELAY;
|
||||
end
|
||||
|
||||
STATE_PTW_READ_MISS_READ_WORD_DELAY: begin
|
||||
SelAdrM = 2'b10;
|
||||
NextState = STATE_PTW_READY;
|
||||
CommittedM = 1'b1;
|
||||
end
|
||||
|
||||
STATE_PTW_ACCESS_AFTER_WALK: begin
|
||||
DCacheStall = 1'b1;
|
||||
SelAdrM = 2'b10;
|
||||
CommittedM = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
|
||||
STATE_CPU_BUSY: begin
|
||||
CommittedM = 1'b1;
|
||||
SelAdrM = 2'b00;
|
||||
@ -608,250 +437,6 @@ module dcachefsm
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// itlb => instruction page fault states with memory request.
|
||||
STATE_PTW_FAULT_READY: begin
|
||||
DCacheStall = 1'b0;
|
||||
LRUWriteEn = 1'b0;
|
||||
SelAdrM = 2'b00;
|
||||
MemAfterIWalkDone = 1'b0;
|
||||
SetDirty = 1'b0;
|
||||
LRUWriteEn = 1'b0;
|
||||
CntReset = 1'b0;
|
||||
AHBWrite = 1'b0;
|
||||
AHBRead = 1'b0;
|
||||
CommittedM = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
|
||||
/// *** BUG BUG BUG missing AMO states.
|
||||
|
||||
// read hit valid cached
|
||||
if(MemRWM[1] & CacheableM & CacheHit & ~DTLBMissM) begin
|
||||
DCacheStall = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
|
||||
if(StallWtoDCache) begin
|
||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
||||
SelAdrM = 2'b10;
|
||||
end
|
||||
else begin
|
||||
MemAfterIWalkDone = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
|
||||
// write hit valid cached
|
||||
else if (MemRWM[0] & CacheableM & CacheHit & ~DTLBMissM) begin
|
||||
SelAdrM = 2'b10;
|
||||
DCacheStall = 1'b0;
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SetDirty = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
|
||||
if(StallWtoDCache) begin
|
||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
||||
SelAdrM = 2'b10;
|
||||
end
|
||||
else begin
|
||||
MemAfterIWalkDone = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
// read or write miss valid cached
|
||||
else if((|MemRWM) & CacheableM & ~CacheHit & ~DTLBMissM) begin
|
||||
NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
|
||||
CntReset = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
end
|
||||
// uncached write
|
||||
else if(MemRWM[0] & ~CacheableM & ~DTLBMissM) begin
|
||||
NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
|
||||
CntReset = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
AHBWrite = 1'b1;
|
||||
end
|
||||
// uncached read
|
||||
else if(MemRWM[1] & ~CacheableM & ~DTLBMissM) begin
|
||||
NextState = STATE_PTW_FAULT_UNCACHED_READ;
|
||||
CntReset = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
AHBRead = 1'b1;
|
||||
MemAfterIWalkDone = 1'b0;
|
||||
end
|
||||
// fault
|
||||
else begin
|
||||
MemAfterIWalkDone = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_FAULT_CPU_BUSY: begin
|
||||
CommittedM = 1'b1;
|
||||
if(StallWtoDCache) begin
|
||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
||||
MemAfterIWalkDone = 1'b0;
|
||||
SelAdrM = 2'b10;
|
||||
end
|
||||
else begin
|
||||
MemAfterIWalkDone = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
SelAdrM = 2'b00;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_FAULT_MISS_FETCH_WDV: begin
|
||||
DCacheStall = 1'b1;
|
||||
PreCntEn = 1'b1;
|
||||
AHBRead = 1'b1;
|
||||
SelAdrM = 2'b10;
|
||||
CommittedM = 1'b1;
|
||||
|
||||
if(FetchCountFlag & AHBAck) begin
|
||||
NextState = STATE_PTW_FAULT_MISS_FETCH_DONE;
|
||||
end else begin
|
||||
NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_FAULT_MISS_FETCH_DONE: begin
|
||||
DCacheStall = 1'b1;
|
||||
SelAdrM = 2'b10;
|
||||
CntReset = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
if(VictimDirty) begin
|
||||
NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
|
||||
end else begin
|
||||
NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK: begin
|
||||
SRAMBlockWriteEnableM = 1'b1;
|
||||
DCacheStall = 1'b1;
|
||||
NextState = STATE_PTW_FAULT_MISS_READ_WORD;
|
||||
SelAdrM = 2'b10;
|
||||
SetValid = 1'b1;
|
||||
ClearDirty = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
|
||||
end
|
||||
|
||||
STATE_PTW_FAULT_MISS_READ_WORD: begin
|
||||
SelAdrM = 2'b10;
|
||||
DCacheStall = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
if(MemRWM[1]) begin
|
||||
NextState = STATE_PTW_FAULT_MISS_READ_WORD_DELAY;
|
||||
// delay state is required as the read signal MemRWM[1] is still high when we
|
||||
// return to the ready state because the cache is stalling the cpu.
|
||||
end else begin
|
||||
NextState = STATE_PTW_FAULT_MISS_WRITE_WORD;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_FAULT_MISS_READ_WORD_DELAY: begin
|
||||
CommittedM = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
if(StallWtoDCache) begin
|
||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
||||
SelAdrM = 2'b10;
|
||||
MemAfterIWalkDone = 1'b0;
|
||||
end
|
||||
else begin
|
||||
MemAfterIWalkDone = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
SelAdrM = 2'b00;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_FAULT_MISS_WRITE_WORD: begin
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
SetDirty = 1'b1;
|
||||
SelAdrM = 2'b10;
|
||||
DCacheStall = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
LRUWriteEn = 1'b1;
|
||||
NextState = STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY;
|
||||
end
|
||||
|
||||
STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY: begin
|
||||
CommittedM = 1'b1;
|
||||
if(StallWtoDCache) begin
|
||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
||||
MemAfterIWalkDone = 1'b0;
|
||||
SelAdrM = 2'b10;
|
||||
end
|
||||
else begin
|
||||
MemAfterIWalkDone = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
SelAdrM = 2'b00;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_FAULT_MISS_EVICT_DIRTY: begin
|
||||
DCacheStall = 1'b1;
|
||||
PreCntEn = 1'b1;
|
||||
AHBWrite = 1'b1;
|
||||
SelAdrM = 2'b10;
|
||||
CommittedM = 1'b1;
|
||||
SelEvict = 1'b1;
|
||||
if(FetchCountFlag & AHBAck) begin
|
||||
NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
|
||||
end else begin
|
||||
NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
STATE_PTW_FAULT_UNCACHED_WRITE : begin
|
||||
DCacheStall = 1'b1;
|
||||
AHBWrite = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
if(AHBAck) begin
|
||||
NextState = STATE_PTW_FAULT_UNCACHED_WRITE_DONE;
|
||||
end else begin
|
||||
NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_FAULT_UNCACHED_READ : begin
|
||||
DCacheStall = 1'b1;
|
||||
AHBRead = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
if(AHBAck) begin
|
||||
NextState = STATE_PTW_FAULT_UNCACHED_READ_DONE;
|
||||
end else begin
|
||||
NextState = STATE_PTW_FAULT_UNCACHED_READ;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_FAULT_UNCACHED_WRITE_DONE: begin
|
||||
CommittedM = 1'b1;
|
||||
if(StallWtoDCache) begin
|
||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
||||
MemAfterIWalkDone = 1'b0;
|
||||
SelAdrM = 2'b10;
|
||||
end
|
||||
else begin
|
||||
MemAfterIWalkDone = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
SelAdrM = 2'b00;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_PTW_FAULT_UNCACHED_READ_DONE: begin
|
||||
CommittedM = 1'b1;
|
||||
SelUncached = 1'b1;
|
||||
if(StallWtoDCache) begin
|
||||
NextState = STATE_PTW_FAULT_CPU_BUSY;
|
||||
SelAdrM = 2'b10;
|
||||
end
|
||||
else begin
|
||||
MemAfterIWalkDone = 1'b1;
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_FLUSH: begin
|
||||
DCacheStall = 1'b1;
|
||||
CommittedM = 1'b1;
|
||||
|
||||
@ -107,8 +107,8 @@ module lsu
|
||||
logic [1:0] MemRWMtoLRSC;
|
||||
logic [2:0] Funct3MtoDCache;
|
||||
logic [1:0] AtomicMtoDCache;
|
||||
logic [`PA_BITS-1:0] MemPAdrMtoDCache;
|
||||
logic [11:0] MemAdrEtoDCache;
|
||||
logic [`PA_BITS-1:0] MemPAdrNoTranslate;
|
||||
logic [11:0] MemAdrE, MemAdrE_RENAME;
|
||||
logic StallWtoDCache;
|
||||
logic MemReadM;
|
||||
logic DataMisalignedMfromDCache;
|
||||
@ -127,9 +127,6 @@ module lsu
|
||||
logic AnyCPUReqM;
|
||||
logic MemAfterIWalkDone;
|
||||
|
||||
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
|
||||
|
||||
|
||||
typedef enum {STATE_T0_READY,
|
||||
STATE_T0_REPLAY,
|
||||
STATE_T0_FAULT_REPLAY,
|
||||
@ -142,8 +139,11 @@ module lsu
|
||||
logic InterlockStall;
|
||||
logic SelReplayCPURequest;
|
||||
logic WalkerInstrPageFaultRaw;
|
||||
logic IgnoreRequest;
|
||||
|
||||
|
||||
|
||||
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (reset) CurrState <= #1 STATE_T0_READY;
|
||||
else CurrState <= #1 NextState;
|
||||
@ -226,9 +226,10 @@ module lsu
|
||||
(CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultF) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
|
||||
|
||||
// When replaying CPU memory request after PTW select the IEUAdrM for correct address.
|
||||
assign SelReplayCPURequest = NextState == STATE_T0_READY;
|
||||
assign SelReplayCPURequest = NextState == STATE_T0_REPLAY;
|
||||
assign SelPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
|
||||
(CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
|
||||
assign IgnoreRequest = CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM);
|
||||
|
||||
|
||||
|
||||
@ -284,8 +285,8 @@ module lsu
|
||||
.MemRWMtoLRSC(MemRWMtoLRSC),
|
||||
.Funct3MtoDCache(Funct3MtoDCache),
|
||||
.AtomicMtoDCache(AtomicMtoDCache),
|
||||
.MemPAdrMtoDCache(MemPAdrMtoDCache),
|
||||
.MemAdrEtoDCache(MemAdrEtoDCache),
|
||||
.MemPAdrNoTranslate(MemPAdrNoTranslate),
|
||||
.MemAdrE(MemAdrE),
|
||||
.StallWtoDCache(StallWtoDCache),
|
||||
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
|
||||
.CommittedMfromDCache(CommittedMfromDCache),
|
||||
@ -295,7 +296,7 @@ module lsu
|
||||
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
|
||||
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
||||
.PrivilegeModeW, .DisableTranslation(DisableTranslation),
|
||||
.PAdr(MemPAdrMtoDCache),
|
||||
.PAdr(MemPAdrNoTranslate),
|
||||
.VAdr(IEUAdrM),
|
||||
.Size(Funct3MtoDCache[1:0]),
|
||||
.PTE(PTE),
|
||||
@ -334,9 +335,9 @@ module lsu
|
||||
always_comb
|
||||
case(Funct3MtoDCache[1:0])
|
||||
2'b00: DataMisalignedMfromDCache = 0; // lb, sb, lbu
|
||||
2'b01: DataMisalignedMfromDCache = MemPAdrMtoDCache[0]; // lh, sh, lhu
|
||||
2'b10: DataMisalignedMfromDCache = MemPAdrMtoDCache[1] | MemPAdrMtoDCache[0]; // lw, sw, flw, fsw, lwu
|
||||
2'b11: DataMisalignedMfromDCache = |MemPAdrMtoDCache[2:0]; // ld, sd, fld, fsd
|
||||
2'b01: DataMisalignedMfromDCache = MemPAdrNoTranslate[0]; // lh, sh, lhu
|
||||
2'b10: DataMisalignedMfromDCache = MemPAdrNoTranslate[1] | MemPAdrNoTranslate[0]; // lw, sw, flw, fsw, lwu
|
||||
2'b11: DataMisalignedMfromDCache = |MemPAdrNoTranslate[2:0]; // ld, sd, fld, fsd
|
||||
endcase
|
||||
|
||||
// Determine if address is valid
|
||||
@ -347,6 +348,8 @@ module lsu
|
||||
// 1. ram // controlled by `MEM_DTIM
|
||||
// 2. cache `MEM_DCACHE
|
||||
// 3. wire pass-through
|
||||
assign MemAdrE_RENAME = SelReplayCPURequest ? IEUAdrM[11:0] : MemAdrE[11:0];
|
||||
|
||||
dcache dcache(.clk(clk),
|
||||
.reset(reset),
|
||||
.StallWtoDCache(StallWtoDCache),
|
||||
@ -355,9 +358,9 @@ module lsu
|
||||
.Funct7M(Funct7M),
|
||||
.FlushDCacheM,
|
||||
.AtomicM(AtomicMtoDCache),
|
||||
.IEUAdrE(MemAdrEtoDCache),
|
||||
.MemAdrE(MemAdrE_RENAME),
|
||||
.MemPAdrM(MemPAdrM),
|
||||
.VAdr(IEUAdrM[11:0]),
|
||||
.VAdr(IEUAdrM[11:0]), // this will be removed once the dcache hptw interlock is removed.
|
||||
.WriteDataM(WriteDataM),
|
||||
.ReadDataM(ReadDataM),
|
||||
.DCacheStall(DCacheStall),
|
||||
@ -365,16 +368,10 @@ module lsu
|
||||
.DCacheMiss,
|
||||
.DCacheAccess,
|
||||
.ExceptionM(ExceptionM),
|
||||
.IgnoreRequest,
|
||||
.PendingInterruptM(PendingInterruptMtoDCache),
|
||||
.DTLBMissM(DTLBMissM),
|
||||
.CacheableM(CacheableMtoDCache),
|
||||
.DTLBWriteM(DTLBWriteM),
|
||||
.ITLBWriteF(ITLBWriteF),
|
||||
.ITLBMissF,
|
||||
.MemAfterIWalkDone,
|
||||
.SelPTW,
|
||||
.WalkerPageFaultM(WalkerPageFaultM),
|
||||
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
|
||||
|
||||
// AHB connection
|
||||
.AHBPAdr(DCtoAHBPAdrM),
|
||||
|
||||
@ -52,8 +52,8 @@ module lsuArb
|
||||
output logic [1:0] MemRWMtoLRSC,
|
||||
output logic [2:0] Funct3MtoDCache,
|
||||
output logic [1:0] AtomicMtoDCache,
|
||||
output logic [`PA_BITS-1:0] MemPAdrMtoDCache,
|
||||
output logic [11:0] MemAdrEtoDCache,
|
||||
output logic [`PA_BITS-1:0] MemPAdrNoTranslate, // THis name is very bad. need a better name. This is the raw address from either the ieu or the hptw.
|
||||
output logic [11:0] MemAdrE,
|
||||
output logic StallWtoDCache,
|
||||
output logic PendingInterruptMtoDCache,
|
||||
|
||||
@ -83,8 +83,8 @@ module lsuArb
|
||||
|
||||
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
|
||||
assign IEUAdrMExt = {2'b00, IEUAdrM};
|
||||
assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0];
|
||||
assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];
|
||||
assign MemPAdrNoTranslate = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0];
|
||||
assign MemAdrE = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];
|
||||
assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
|
||||
// always block interrupts when using the hardware page table walker.
|
||||
assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user