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Author	SHA1	Message	Date
Jordan Carlin	d58b454a8b	Finish switching Zfa to use riscv-arch-test	2024-06-18 23:31:37 -07:00
Jordan Carlin	00ccd80479	Update VCS RTL file exclusions with renamed ram	2024-06-18 22:47:00 -07:00
Jordan Carlin	955f5d831f	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-06-18 22:39:05 -07:00
Rose Thompson	d2933edee4	Merge pull request #836 from davidharrishmc/dev ... Code Cleanup: Lint Improvements	2024-06-18 08:56:17 -07:00
David Harris	301ded05f8	Unused signal cleanup	2024-06-18 08:15:48 -07:00
David Harris	cb563e8018	Clean up unused signals	2024-06-18 08:07:14 -07:00
David Harris	c1fd7a9589	Removed unused signals	2024-06-18 07:28:52 -07:00
Jordan Carlin	a493b9b131	Merge pull request #835 from davidharrishmc/dev ... Fixed Issue #752 of Verilator simulation by changing LRUMemory to be …	2024-06-18 07:27:35 -07:00
David Harris	8bae52b09d	Lint cleanup of unused signals	2024-06-18 06:49:17 -07:00
David Harris	45f505250c	Lint cleanup	2024-06-18 06:23:43 -07:00
David Harris	3fa37b0233	Lint cleanup	2024-06-18 06:15:17 -07:00
David Harris	cac67aae4f	Lint cleanup	2024-06-18 05:58:54 -07:00
David Harris	ecae1100f6	Lint cleanup	2024-06-18 05:49:49 -07:00
David Harris	7509e856df	Removed asynchronous reset causing lint issue in peripherals	2024-06-18 05:49:12 -07:00
David Harris	2fc9edff45	Fixed Issue #752 of Verilator simulation by changing LRUMemory to be nonblocking now that Verilator handles this construct properly	2024-06-18 04:40:38 -07:00
Matthew	5c593c3321	Fix step timing, rewrite jtag to include explicit reset	2024-06-17 10:51:22 -05:00
Matthew	7dd0182407	add progbuff write logic stub	2024-06-16 15:21:02 -05:00
Matthew	c853eeec9c	fix typo in csrd	2024-06-16 11:44:05 -05:00
Matthew	d6256d1647	cleanup, dont update Prv in DCSR	2024-06-15 22:54:10 -05:00
James Stine	3a2e8ae3cc	just in case: add rad.sv with comment + new cfg for openocd	2024-06-15 22:01:49 -05:00
Matthew	679ff3455b	Improved permissions for CSR access	2024-06-14 23:18:34 -05:00
Rose Thompson	54c07265ba	Merge pull request #833 from davidharrishmc/dev ... Code cleanup in anticipation of code review	2024-06-14 21:06:47 -07:00
Matthew	60f12a6f60	Fix DPC write and DCSR Cause	2024-06-14 18:27:06 -05:00
Matthew	d0deb1bd7a	Add DPC support (does not write on resume)	2024-06-14 14:21:38 -05:00
David Harris	4a4bbdfc43	More code cleanup	2024-06-14 09:50:07 -07:00
Matthew	be7d657f71	Fix CSR writes from DM	2024-06-14 11:17:41 -05:00
David Harris	bfd3c9fe86	Fixed gettenvval when variable is undefined per verilator Issue 5179	2024-06-14 07:09:53 -07:00
David Harris	53477b2c85	Code cleanup	2024-06-14 07:08:17 -07:00
David Harris	8f09240e6c	Simplified outdated documentation pointers	2024-06-14 03:42:15 -07:00
David Harris	b1c9450b4a	Code cleanup: RAM, fdivsqrt	2024-06-14 03:35:05 -07:00
David Harris	6789f32154	Starting code cleanup	2024-06-14 02:54:43 -07:00
David Harris	334b616d6f	Removed redundant apt-get line	2024-06-14 02:52:27 -07:00
David Harris	fb75fe461c	Remove stale questa wkdir before regression	2024-06-14 02:51:55 -07:00
Matthew	6ae7ac9a6d	Implement DCSR (Writes are broken)	2024-06-14 00:35:20 -05:00
Matthew	d319703d75	update jtag id	2024-06-13 23:22:39 -05:00
Rose Thompson	b77fcd70e6	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-06-13 13:58:07 -05:00
Matthew-Otto	f3ff6712c9	Merge branch 'openhwgroup:main' into main	2024-06-12 22:43:10 -05:00
Matthew	d21e5b1fca	fix scanning when XLEN != FLEN	2024-06-12 22:41:48 -05:00
Matthew	61eba041e4	fix whitespace in fregfile.sv	2024-06-12 22:27:25 -05:00
Matthew	6f1f3b719a	Alls CSRS tested (Read only)	2024-06-12 10:28:42 -05:00
Matthew	31f437b429	fixed GPR/FPR scan regression	2024-06-12 10:10:32 -05:00
David Harris	312c9c9f55	Updated logger to new IClass signal name	2024-06-12 07:24:05 -07:00
David Harris	28142eff64	Formatting shiftcorrection	2024-06-12 04:25:13 -07:00
David Harris	544aa7cd8d	shiftcorrection cleanup	2024-06-12 04:13:51 -07:00
David Harris	b7e2f34966	shiftcorrection cleanup	2024-06-12 03:59:55 -07:00
Matthew	c8e5a33ae7	cleanup repo, still WIP	2024-06-11 23:04:44 -05:00
Matthew	abff0bbab4	(WIP) make all CSRs scannable by DM	2024-06-11 22:42:30 -05:00
Rose Thompson	46cc64b76f	Merge pull request #830 from davidharrishmc/dev ... Regression improvement and FPU simplification	2024-06-11 13:18:11 -07:00
David Harris	29fe5983e2	Fixed testfloat regression and added bitmanip/crypto variants	2024-06-11 12:32:11 -07:00
James Stine	f5e22fccbb	update csrm to add dpc and dcsr	2024-06-10 17:31:14 -05:00