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just in case: add rad.sv with comment + new cfg for openocd

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This commit is contained in:
James Stine 2024-06-15 22:01:49 -05:00
parent 679ff3455b
commit 3a2e8ae3cc
2 changed files with 5 additions and 2 deletions
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5
src/debug/rad.sv
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@ -110,7 +110,10 @@ module rad import cvw::*; #(parameter cvw_t P) (
`MIP_REGNO : begin
ShiftCount = P.LLEN - 1;
CSRegNo = 1;
RegReadOnly = 1;
// Comment out because gives error on openocd
// This value cause the csrs to all go read-only
// which openocd doesnt like
//RegReadOnly = 1;
end
[`HPMCOUNTERBASE_REGNO:`TIME_REGNO],

2
tests/debug/simple/openocd.cfg
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@ -22,7 +22,7 @@ adapter speed 1000
#ftdi tdo_sample_edge falling
set _CHIPNAME cvw
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1002A005
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1002AC05
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME