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10,550 Commits 4 Branches 2 Tags 52 MiB
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452 Commits

Author SHA1 Message Date
Rose Thompson
78e11ed9f3 Remove old unused file. 2024-12-02 15:24:46 -06:00
Rose Thompson
7358c1fe67 Fixed sublte bug in the spi_fifo which allows for spurious write to fifo. Fixed fpga zsbl so that is uses read fifo interrupt pending (IP) rather than transmit fifo IP. Resolves issue with stalled load reading the wrong fifo status. 2024-11-25 15:50:29 -06:00
Rose Thompson
88745e27d3 Fixed ila after updates. 2024-11-13 12:57:02 -06:00
Rose Thompson
d5e8ecbed5 Simplified the fpgatop SDCCLK logic. 2024-11-12 15:29:05 -06:00
Rose Thompson
827f986fae This configuration of the vcu108 actually seems to work. 2024-11-05 16:01:08 -06:00
Rose Thompson
aaf36d11b5 Now have the vcu108 kind of working with the new spi controller. However, it still has issues mounting the ext4 partition. 2024-11-05 15:20:53 -06:00
Jacob Pease
9c39371657 Reverted bootloader optimizations to second iteration. Working on last optimization. 2024-11-02 14:14:31 -05:00
Rose Thompson
57d1709582 The path to the zsbl was wrong all this time, but for reason was working with older versions of Ubuntu, but one 24.04 it causes vivado to not find the rom and ram. 2024-10-30 16:01:11 -05:00
Jordan Carlin
05d86fc6ce
Update fpga README formatting 2024-10-17 15:08:32 -07:00
Rose Thompson
8fb1673ab3 Updated email address authorship for my files. 2024-10-15 10:27:53 -05:00
Rose Thompson
d4fc3245b0 Removed ahbsdc submodule since it is no longer used. Updated old 
submodules pointing to ross144 to rosethompson repos.
 2024-10-15 10:11:12 -05:00
Rose Thompson
fed88f6b17 Better formatting for readme. 2024-10-14 22:10:28 -05:00
Rose Thompson
cdc0ecc87c FPGA readme now in markdown. 2024-10-14 22:08:09 -05:00
Rose Thompson
86ec7f609b Updated FPGA readme. 2024-10-14 22:06:38 -05:00
Rose Thompson
816e54f451 Revert "Revmoed file from fpga zbbl which should not have been added." 
This reverts commit d6944cdaa4.
 2024-10-14 21:29:02 -05:00
Rose Thompson
d6944cdaa4 Revmoed file from fpga zbbl which should not have been added. 2024-10-03 15:03:15 -05:00
Jordan Carlin
6d21e272d0
Remove fpga bootrom.txt 2024-10-01 12:19:12 -07:00
Jordan Carlin
bcbc2f2eed
Remove fpga/sim 2024-10-01 12:18:54 -07:00
Jordan Carlin
47d7849554
Remove more old files 2024-09-30 10:44:36 -07:00
Jordan Carlin
022b98a64b
Update all iterative makes to use 2024-09-29 23:14:19 -07:00
Rose Thompson
1345a0f315 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-09-24 10:13:50 -05:00
James Stine
c8921250db remove hard-code path in wave_config.wcfg even though its probably not needed. Its a generated file. I believe the path doesn't matter, so I removed it. 2024-09-18 15:40:00 -05:00
Rose Thompson
510e3a268c Added spi debugger to build script. 2024-09-05 12:04:14 -07:00
Rose Thompson
261e503061 Updates for arty A7 device tree. 2024-09-05 12:02:07 -07:00
Rose Thompson
8c99e28c8b Fixed bugs in the fpga Makefile and vcu118 ddr memory gen script. 2024-09-03 21:03:38 -07:00
Rose Thompson
f22f056b09 This actually fixes the vcu108 to correctly set the SPI clock frequency. 2024-09-03 13:11:03 -07:00
Rose Thompson
c24d061d0a Fixed typo in fpga Makefile. 2024-09-03 12:19:16 -07:00
Rose Thompson
8248f2dd66 Added MAXSDCCLOCK to parameters set by the FPGA makefile. 2024-09-03 10:55:15 -07:00
Rose Thompson
d0ae6bf217 Fixed type in fpga Makefile 2024-09-03 10:36:49 -07:00
Rose Thompson
cde4598ed5 Updated vcu108 and vcu118 scripts to corrects set the clock speed. 2024-09-03 10:31:55 -07:00
Rose Thompson
702fa4e7bd Finally worked out that subtle bug in the tcl scripts clock setting. 2024-09-03 10:30:34 -07:00
Rose Thompson
e29e1feed5 Corrects merge error in Arty A7 clock speed. 2024-09-02 15:01:41 -07:00
Rose Thompson
8375e168c0 Removed file accidently readded. 2024-09-02 14:48:36 -07:00
Rose Thompson
3a0e28fea0 Added missing spi debugger. 2024-09-02 14:47:31 -07:00
Rose Thompson
4afdb500d7 Added missing files. 2024-09-02 14:46:41 -07:00
Rose Thompson
d5e0382a81 vcu108 build now starts with make vcu108 and selects the correct 
memory size, starting address, device tree location, and clock speed
for the zsbl and synthesis scripts.
 2024-09-02 14:23:16 -07:00
Rose Thompson
869860bc55 Merge branch 'main' of github.com:ross144/cvw 2024-09-02 14:08:48 -07:00
Rose Thompson
9471ccd2fc Updated Makefiles and source files to build the zsbl according to the config. 2024-09-02 14:03:47 -07:00
Rose Thompson
2e55f1cecc Well on the way to a fully automated FPGA build process which 
correctly sets the clocks and memory locations.
 2024-09-02 11:19:02 -07:00
Jacob Pease
4b8d35bd8a Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-30 14:18:54 -05:00
Jacob Pease
4acac08320 Fixed Arty constraints and corrected typos. 2024-08-30 14:17:37 -05:00
Rose Thompson
f1d9e18dee Modified fpga config to support two fpga boards with different amount of memory. 
Modified vcu108 constraints to better constrain the spi clock and in/out.
 2024-08-29 16:12:58 -07:00
Rose Thompson
0ce4d1b452 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-29 10:50:27 -07:00
Rose Thompson
7e16ddd859 Improved fpga synth script. 2024-08-27 15:50:05 -07:00
Rose Thompson
e5d3462a90 Converted wall.tcl to entirely project mode. 2024-08-27 14:15:58 -07:00
Jacob Pease
44ece7cb96 Added CVW header to spitest files. 2024-08-27 14:28:49 -05:00
Rose Thompson
f20a1564fa Added SPI debugger. 2024-08-26 17:22:13 -07:00
Jacob Pease
d649473ec8 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-24 21:57:44 -05:00
Jacob Pease
ad6734eb6d Improved the speed of the bootloader by 60s. CRC16 is now calculated with a table and a byte is now sent for every byte read, keeping the FIFO full. 2024-08-24 21:36:29 -05:00
Rose Thompson
ee1e09a6a2 VCU108 now boot linux at 50MHz! 2024-08-23 17:18:47 -07:00