277 Commits

Author	SHA1	Message	Date
Ross Thompson	f87a6f2c63	More cache cleanup.	2022-02-13 12:38:39 -06:00
Ross Thompson	f5c4bca47e	Formating improvements to cache.	2022-02-11 23:10:58 -06:00
Ross Thompson	6fa9490d0b	More cache simplifications.	2022-02-11 22:54:05 -06:00
Ross Thompson	ae2011eb07	Reduced seladr to 1 bit as second bit is same as selflush.	2022-02-11 22:41:36 -06:00
Ross Thompson	cb3d71a63d	Reduced complexity of the address selection during flush.	2022-02-11 22:27:27 -06:00
Ross Thompson	a0ee2f3d99	Removed redundant signals from cache.	2022-02-11 22:23:47 -06:00
Ross Thompson	aa04778d0b	Cache fsm simplifications.	2022-02-11 15:16:45 -06:00
Ross Thompson	e6c8cfd49b	Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.	2022-02-11 15:09:00 -06:00
Ross Thompson	83adacbee3	Simplified cache fsm.	2022-02-11 14:54:57 -06:00
Ross Thompson	c8e6884926	Fixed bug. ... It was possible for DTLBMissM to prevent a dcache flush.	2022-02-11 14:00:01 -06:00
Ross Thompson	b1cba4be2b	Updates to linux wave.	2022-02-11 13:28:18 -06:00
Ross Thompson	9145a96b53	Updated linux wave.	2022-02-11 13:15:42 -06:00
Ross Thompson	3f4ae91468	linux wave cleanup.	2022-02-11 10:48:45 -06:00
Ross Thompson	20456097cd	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-11 10:47:21 -06:00
Ross Thompson	2f2a4f4500	Fixed subtle and infrequenct bug. ... Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.	2022-02-11 10:46:06 -06:00
David Harris	15fb7fee60	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
Ross Thompson	fc6dc52618	Fixed bugs in ifu spills and missing reset on bus data register.	2022-02-10 18:11:57 -06:00
Ross Thompson	9ad4523b9d	Updated wave files to reflect recent changes.	2022-02-10 17:52:19 -06:00
Ross Thompson	f23817bf69	Replacement policy cleanup.	2022-02-10 11:42:40 -06:00
Ross Thompson	411997010b	Replacement policy cleanup.	2022-02-10 11:40:10 -06:00
Ross Thompson	382d5fab0f	Cleanup.	2022-02-10 11:27:15 -06:00
Ross Thompson	3a0af5d9e9	Cleanup + critical path optimizations.	2022-02-10 11:11:16 -06:00
Ross Thompson	fc68c2f09a	Cache name clarifications.	2022-02-10 10:50:17 -06:00
Ross Thompson	e00d404154	More cache cleanup.	2022-02-10 10:43:37 -06:00
Ross Thompson	65803ebe98	structural muxes.	2022-02-09 19:36:21 -06:00
Ross Thompson	2a989e6d05	More cache cleanup.	2022-02-09 19:29:15 -06:00
Ross Thompson	3b8ad3f7c7	Cleaned up comments.	2022-02-09 19:21:35 -06:00
Ross Thompson	911ee36b22	Removed all possilbe paths to PreSelAdr from TrapM.	2022-02-09 19:20:10 -06:00
Ross Thompson	327a05c9d8	Added commented out commands to generate saif file from vsim.	2022-02-09 18:40:45 -06:00
Ross Thompson	01126535db	Annotated the final changes required to move sram address off the critial path.	2022-02-08 18:17:31 -06:00
Ross Thompson	7133e790ea	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 17:52:15 -06:00
Ross Thompson	498388c636	Cache cleanup write enables.	2022-02-08 17:52:09 -06:00
Ross Thompson	8a49ec90d0	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 15:43:18 -06:00
Ross Thompson	e0a605e95d	Cleanup IFU.	2022-02-08 14:54:53 -06:00
Ross Thompson	d1d014bf1d	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 14:47:15 -06:00
Ross Thompson	13561c67bd	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 14:22:19 -06:00
Ross Thompson	cecbb3362d	rv32e works for now. Still need to optimize.	2022-02-08 14:21:55 -06:00
Ross Thompson	39149c618f	Moved some muxes back into the bp.	2022-02-08 14:17:44 -06:00
David Harris	3e16730226	RAM simplification	2022-02-08 20:15:23 +00:00
Ross Thompson	d5d9bb9d4d	Temporary commit which gets the no branch predictor implementation working.	2022-02-08 14:13:55 -06:00
David Harris	c07584bb70	rv32e config update	2022-02-08 17:59:50 +00:00
Ross Thompson	c2377eaaf4	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 11:36:30 -06:00
Ross Thompson	3cd067ac6a	Finished merge.	2022-02-08 11:36:24 -06:00
David Harris	9ad3f26365	Restored E tests to makefrag	2022-02-08 16:41:11 +00:00
Ross Thompson	492c1473f3	Preparing to make a major change to the cache's write enables.	2022-02-08 09:47:01 -06:00
David Harris	e5097e67d4	Fixed TIM tests; rv32e test still failing	2022-02-08 15:24:37 +00:00
David Harris	e9a519a228	Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail	2022-02-08 12:40:02 +00:00
David Harris	096242a6d8	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
David Harris	72c2166223	Lab 3 file cleanup	2022-02-08 10:26:37 +00:00
Ross Thompson	190d619940	cachefsm cleanup.	2022-02-07 22:09:56 -06:00