55 Commits

Author	SHA1	Message	Date
slmnemo	8c3d7b404b	Fixed recurrent issue with testbench where it would never stop	2022-06-03 18:56:24 -07:00
slmnemo	568b83a647	Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do" ... This reverts commit 7d2bfb6db8.	2022-06-02 12:45:21 -07:00
slmnemo	40abe59d33	Revert "Fixed buildroot by adding a second ." ... This reverts commit 0982417054.	2022-06-02 12:43:59 -07:00
slmnemo	35caa03e46	Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files	2022-06-02 02:51:51 +00:00
slmnemo	2f3689063a	Revert Commit 61ebf68939	2022-05-28 03:35:17 -07:00
slmnemo	61ebf68939	Deparametrized Linux testbench and removed mentions of parameters in wally-pipelined.do	2022-05-28 03:14:49 -07:00
slmnemo	a5d5bd272b	changes suggested by ben, hopefully fixing buildroot (which is now not running)	2022-05-20 18:42:38 -07:00
slmnemo	0982417054	Fixed buildroot by adding a second .	2022-05-19 17:49:32 -07:00
slmnemo	7d2bfb6db8	parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do	2022-05-19 16:21:38 -07:00
David Harris	21c1e58829	Partitioned privilege mode fsm into new module	2022-05-12 16:16:42 +00:00
David Harris	e2dea3bb89	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
David Harris	a8c9f504fa	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	91472eb948	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
Skylar Litz	970f6c4222	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-27 10:50:19 -07:00
Skylar Litz	594db170de	fix AttemptedInstructionCount from ground zero	2022-04-27 10:45:40 -07:00
David Harris	0ede295e88	Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields	2022-04-25 14:49:00 +00:00
Ross Thompson	546ef08eb2	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-19 14:09:50 -05:00
Ross Thompson	a99466a487	Fixed bug I introduced by csrc cleanup and changes to ILA.	2022-04-17 21:45:46 -05:00
Ross Thompson	c409bde6ae	fixed no forcing bug in linux testbench.	2022-04-17 17:49:51 -05:00
bbracker	fe53dd1683	fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM	2022-04-14 09:23:21 -07:00
bbracker	eb21e34000	fix ReadDataM forcing	2022-04-13 15:32:00 -07:00
Ross Thompson	2e8afd071e	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-13 13:39:47 -05:00
bbracker	735c75af55	change interrupt spoofing to happen at negative clock edges	2022-04-13 04:31:23 -07:00
bbracker	52ed99ca1b	improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS	2022-04-13 03:37:53 -07:00
bbracker	03f1c01f14	whoops forgot to update AttemptedInstructionCount in interrupt spoofing	2022-04-13 00:49:37 -07:00
bbracker	d3e9703c19	change testbench-linux to by default use attempted instruction count for warning/error messages	2022-04-12 21:22:08 -07:00
Ross Thompson	fc173a7954	Missed the force on uart for no tracking.	2022-04-12 19:37:44 -05:00
Ross Thompson	f995ec2a54	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-10 13:41:27 -05:00
Ross Thompson	c3d9eafe60	Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.	2022-04-10 13:27:54 -05:00
bbracker	aa71fe542d	upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs	2022-04-08 13:45:27 -07:00
bbracker	3b6cb5f0ba	small signs of life on new interrupt spoofing	2022-04-08 12:32:30 -07:00
bbracker	54b9745a75	big interrupts refactor	2022-03-30 13:22:41 -07:00
Ross Thompson	3ac736e2d5	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-30 11:09:44 -05:00
Ross Thompson	fc2b4453ec	rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.	2022-03-29 23:48:19 -05:00
Skylar Litz	29d1f64588	add AtemptedInstructionCount signal	2022-03-26 21:28:57 +00:00
bbracker	b08066381a	fix multiple-context PLIC checkpoint generation	2022-03-25 01:02:22 +00:00
bbracker	150a7b234b	tabs vs spaces disagreement	2022-03-24 17:11:41 -07:00
bbracker	9f60256f22	1st attempt at multiple channel PLIC	2022-03-24 17:08:10 -07:00
Ross Thompson	58668812c1	Moved WriteDataM register into LSU.	2022-03-23 14:17:59 -05:00
Ross Thompson	f1787670d4	Cleanup in testbench-linux.sv.	2022-03-22 22:34:38 -05:00
Ross Thompson	7fc128ba7c	added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.	2022-03-22 21:28:34 -05:00
Ross Thompson	80d376877a	Added spoof of uart addresses +0x2 and +0x6.	2022-03-22 16:52:27 -05:00
bbracker	51e68819c4	fix up PLIC and UART checkpointing	2022-03-07 23:48:47 -08:00
bbracker	c2ac18b5de	change testbench-linux.sv to use new shared location of disassembly files	2022-03-07 20:04:08 -08:00
bbracker	5f5cc514b8	fix buildroot checkpointing and add it back to regression	2022-03-02 16:00:19 +00:00
bbracker	04ace8c154	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
David Harris	c12407ba6a	Removed Busybear dependencies	2022-02-02 20:28:21 +00:00
Ross Thompson	c1311ca56a	Fixed modelsim warning with linux simulation.	2022-01-31 12:57:02 -06:00
David Harris	2d112698b7	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
David Harris	ca1f7ce5d3	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00