78 Commits

Author	SHA1	Message	Date
David Harris	f57096a5d2	Restored to working multiplier after Lab 2	2021-02-25 15:32:43 -05:00
David Harris	cd4ba8831c	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	38b8cc652c	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
Katherine Parry	07641203ee	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-23 20:21:53 +00:00
Katherine Parry	906ec30339	inital FMA push	2021-02-23 20:19:12 +00:00
David Harris	7737b0f709	Fixed fetch stall after jump in bus unit	2021-02-23 09:08:57 -05:00
David Harris	f372e2b8e8	Debugging Bus interface	2021-02-22 13:48:30 -05:00
David Harris	87ad559a90	Updated creation date of mul	2021-02-18 08:13:08 -05:00
David Harris	fe7299c155	Resotred part of multiplier for lab 2	2021-02-17 16:14:04 -05:00
David Harris	492ec0ee78	Removed multiplier for lab 2	2021-02-17 16:06:16 -05:00
David Harris	e8d3c7d9e7	Multiplier tweaks	2021-02-17 16:00:27 -05:00
David Harris	e64e8afb7f	Started to integrate OSU divider	2021-02-17 15:38:44 -05:00
David Harris	a7dd20b388	Multiply instructions working	2021-02-17 15:29:20 -05:00
David Harris	adc5d5bc1a	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	cc42655789	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
bbracker	deb7780897	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00
David Harris	b121b90b28	Debugging bus interface.	2021-02-10 01:43:54 -05:00
David Harris	842c374de9	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	74bc4c0444	Fixed lw by delaying read value by one cycle	2021-02-07 23:28:21 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
Brett Mathis	11e2666bb2	Parallel FSR's and F CTRL logic	2021-02-04 02:25:55 -06:00
David Harris	2a80bcf543	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-02 19:44:43 -05:00
David Harris	756352f129	Minor tweaks	2021-02-02 19:44:37 -05:00
Noah Boorstin	b5f474d9f5	same thing but do that right this time	2021-02-02 21:47:15 +00:00
Noah Boorstin	6dd5c42d55	change undefined syntax in extend.sv ... don't need verilator execption anymore	2021-02-02 21:39:20 +00:00
David Harris	429f48e766	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	9f9c3bcece	Changed DTIM latency to 2 cycles	2021-02-02 14:22:12 -05:00
David Harris	616830a3f0	Cleaned up hazard interface	2021-02-02 13:53:13 -05:00
David Harris	229bde5953	Moved LoadStall generation to IEU	2021-02-02 13:42:23 -05:00
David Harris	bb83fda1d8	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
Brett Mathis	bcb722272e	OSU FPU IP initial commit	2021-02-01 19:33:43 -06:00
David Harris	1a3963bed0	Renamed DCU to DMEM	2021-02-01 18:52:22 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
David Harris	29313a108b	Working on reading instruction from TIM	2021-01-30 01:57:51 -05:00
David Harris	5429424871	Adding stalls for memory delays	2021-01-30 01:43:49 -05:00
David Harris	26c560fba3	Added HCLK and HRESETn	2021-01-30 00:56:12 -05:00
David Harris	9511dcac84	Connected AHB bus to Uncore	2021-01-29 23:43:48 -05:00
David Harris	9297376873	Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team	2021-01-29 18:06:36 -05:00
David Harris	6c76962847	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-01-29 17:29:01 -05:00
David Harris	9530039e3d	Implemented adrdec for uncore	2021-01-29 17:28:53 -05:00
Teo Ene	5e5e03c717	- Removed latch on CSRCReadValM in csrc.sv ... - Changed top level to wallypipelinedhart	2021-01-29 15:56:51 -06:00
David Harris	d104e5a4be	Moving data memory to uncore	2021-01-29 15:37:51 -05:00
David Harris	e4e95bf941	Added ahblite bus interface unit	2021-01-29 01:07:17 -05:00
David Harris	aedadb7703	Renamed modules in privileged unit	2021-01-28 23:21:12 -05:00
David Harris	004cc525e2	Hint to optimize ifu	2021-01-28 21:40:48 -05:00
David Harris	1ad69b52d5	Fixed floating signals in clint and ieu	2021-01-28 15:44:05 -05:00
David Harris	8eebf01dca	Fixed c.jr instruction improperly writing ra	2021-01-28 15:18:23 -05:00
David Harris	52d6a01cea	Created DCU and moved memdp into DCU	2021-01-28 01:03:12 -05:00
David Harris	af25784b61	Provided PC + 2 or 4 (PCLink) for JAL	2021-01-28 00:22:05 -05:00