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Author	SHA1	Message	Date
Rose Thompson	f4b5664cc6	Merge branch 'main' of github.com:openhwgroup/cvw	2024-09-03 13:12:00 -07:00
Rose Thompson	f22f056b09	This actually fixes the vcu108 to correctly set the SPI clock frequency.	2024-09-03 13:11:03 -07:00
Rose Thompson	c24d061d0a	Fixed typo in fpga Makefile.	2024-09-03 12:19:16 -07:00
Rose Thompson	8248f2dd66	Added MAXSDCCLOCK to parameters set by the FPGA makefile.	2024-09-03 10:55:15 -07:00
Rose Thompson	d0ae6bf217	Fixed type in fpga Makefile	2024-09-03 10:36:49 -07:00
Rose Thompson	cde4598ed5	Updated vcu108 and vcu118 scripts to corrects set the clock speed.	2024-09-03 10:31:55 -07:00
Rose Thompson	702fa4e7bd	Finally worked out that subtle bug in the tcl scripts clock setting.	2024-09-03 10:30:34 -07:00
David Harris	ff9f0fa140	Updated riscv-isac dependencies for security	2024-09-03 03:46:44 -07:00
David Harris	b670f700ec	Test push	2024-09-03 03:37:33 -07:00
Rose Thompson	e29e1feed5	Corrects merge error in Arty A7 clock speed.	2024-09-02 15:01:41 -07:00
Rose Thompson	8375e168c0	Removed file accidently readded.	2024-09-02 14:48:36 -07:00
Rose Thompson	3a0e28fea0	Added missing spi debugger.	2024-09-02 14:47:31 -07:00
Rose Thompson	4afdb500d7	Added missing files.	2024-09-02 14:46:41 -07:00
Rose Thompson	d5e0382a81	vcu108 build now starts with make vcu108 and selects the correct ... memory size, starting address, device tree location, and clock speed for the zsbl and synthesis scripts.	2024-09-02 14:23:16 -07:00
Rose Thompson	869860bc55	Merge branch 'main' of github.com:ross144/cvw	2024-09-02 14:08:48 -07:00
Rose Thompson	9471ccd2fc	Updated Makefiles and source files to build the zsbl according to the config.	2024-09-02 14:03:47 -07:00
Rose Thompson	2e55f1cecc	Well on the way to a fully automated FPGA build process which ... correctly sets the clocks and memory locations.	2024-09-02 11:19:02 -07:00
Jordan Carlin	0200b08418	Merge pull request #940 from ross144/main ... Merges Jordan's wally.do updates with the new fcov2 changes.	2024-08-30 12:35:11 -07:00
Rose Thompson	65e338e762	Merges Jordan's wally.do updates with the new fcov2 changes. Updates ... cvw-arch-verif commit.	2024-08-30 12:31:26 -07:00
Rose Thompson	6f7d4cde21	Merge pull request #908 from jordancarlin/script_updates ... Sim updates + rv64gcCacheSim.py fixed	2024-08-30 12:25:44 -07:00
Rose Thompson	5fb3b386f5	Merge pull request #939 from JacobPease/main ... Fixed Arty constraints and corrected typos.	2024-08-30 12:23:53 -07:00
Jacob Pease	4b8d35bd8a	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-30 14:18:54 -05:00
Jacob Pease	4acac08320	Fixed Arty constraints and corrected typos.	2024-08-30 14:17:37 -05:00
Jordan Carlin	4929581576	Cleanup	2024-08-30 11:57:31 -07:00
Rose Thompson	f1d9e18dee	Modified fpga config to support two fpga boards with different amount of memory. ... Modified vcu108 constraints to better constrain the spi clock and in/out.	2024-08-29 16:12:58 -07:00
Jordan Carlin	80750f2308	Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates	2024-08-29 15:55:54 -07:00
David Harris	ffd4d71fe5	Merge pull request #938 from ross144/main ... Fixed basic support for open source riscvISACOV	2024-08-29 15:42:40 -07:00
Rose Thompson	587a65aa75	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-29 15:30:45 -07:00
Rose Thompson	e07f303353	Have basic rv32gc functional coverage running with open source riscvISACOV.	2024-08-29 15:29:04 -07:00
David Harris	636a8cbbd6	Merge pull request #937 from ross144/main ... Fixed questa and ImperasDV library issue	2024-08-29 15:00:18 -07:00
Rose Thompson	dc9a77e45a	Updated riscvISACOV submodule to https instead of ssh.	2024-08-29 14:54:47 -07:00
Rose Thompson	a1c6bc854e	Fixed a subtle questa sim bug with imperasDV. On some linux systems ... vsim will default to 32-bit mode rather than 64-bit, but the ImperasDV libraries are 64-bit. vsim must run in 64-bit mode.	2024-08-29 14:00:52 -07:00
Rose Thompson	0ce4d1b452	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-29 10:50:27 -07:00
Rose Thompson	6ad2c2e7a6	Merge pull request #935 from davidharrishmc/dev ... Added lockstep support for RV32. Not all wally privileged tests pass…	2024-08-29 10:45:17 -07:00
David Harris	26f3c2a607	Added lockstep support for RV32. Not all wally privileged tests pass yet	2024-08-29 10:44:37 -07:00
David Harris	ca4dcfdaa9	Merge pull request #934 from JacobPease/main ... Custom test spitest fix	2024-08-28 02:13:06 -07:00
Jacob Pease	c4d909c412	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-28 04:10:38 -05:00
Jacob Pease	3b91977227	Added start.s to spitest directory.	2024-08-28 04:10:24 -05:00
Rose Thompson	cb05697698	Added basic SPI signals to waveform.	2024-08-27 15:51:19 -07:00
Rose Thompson	7e16ddd859	Improved fpga synth script.	2024-08-27 15:50:05 -07:00
Rose Thompson	e5d3462a90	Converted wall.tcl to entirely project mode.	2024-08-27 14:15:58 -07:00
Rose Thompson	0ce289c937	Merge pull request #933 from JacobPease/main ... Committing the custom test spitest.	2024-08-27 12:43:19 -07:00
Jacob Pease	44ece7cb96	Added CVW header to spitest files.	2024-08-27 14:28:49 -05:00
Jacob Pease	b7a74307c5	Committing the custom test spitest.	2024-08-27 14:19:56 -05:00
Rose Thompson	2dd897e7e1	Merge pull request #932 from davidharrishmc/dev ... Added temporary --fcov2 option to start adopting open-source riscvISACOV	2024-08-27 08:47:59 -07:00
David Harris	9df38e14b2	Added temporary --fcov2 option to start adopting open-source riscvISACOV	2024-08-27 08:40:44 -07:00
Rose Thompson	f20a1564fa	Added SPI debugger.	2024-08-26 17:22:13 -07:00
Rose Thompson	f31eb62c1b	Merge pull request #929 from JacobPease/main ... Bootloader Speed Improvements	2024-08-26 09:10:42 -07:00
Jordan Carlin	0c4993e1db	Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates	2024-08-25 14:57:22 -07:00
Jordan Carlin	99da7e7b21	Merge pull request #931 from davidharrishmc/dev ... Fixed imperas configuration and updated files for new Imperas/Synopsy…	2024-08-25 14:55:42 -07:00