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Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates

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Jordan Carlin 2024-08-25 14:57:22 -07:00
commit 0c4993e1db
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3 changed files with 4 additions and 2 deletions
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3
bin/regression-wally
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@ -371,6 +371,7 @@ args = parser.parse_args()
if (args.nightly):
nightMode = "--nightly";
sims = ["questa", "verilator", "vcs"] # exercise all simulators; can omit a sim if no license is available
# sims = ["questa", "verilator"] # exercise all simulators; can omit a sim if no license is available
else:
nightMode = ""
sims = [defaultsim]
@ -512,7 +513,7 @@ def main():
elif args.fcov:
TIMEOUT_DUR = 1*60
os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*')
elif args.nightly:
elif args.buildroot:
TIMEOUT_DUR = 60*1440 # 1 day
elif args.testfloat:
TIMEOUT_DUR = 30*60 # seconds

2
sim/imperas.ic
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@ -74,7 +74,7 @@
--override cpu/PMP_undefined=T
# mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception
--override cpu/mstatus_fs_mode=rvfs_write_nz
--override cpu/mstatus_fs_mode=write_1
# PMA Settings
# 'r': read access allowed

1
site-setup.sh
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@ -11,6 +11,7 @@
# Must edit these based on your local environment.
export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
export IMPERASD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Imperas license server
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin
export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin
export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, excluding bin