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231 Commits

Author SHA1 Message Date
Ross Thompson
de54b5c4d8 Updated wavefile 2023-09-05 11:11:56 -05:00
David Harris
9747d122d2 tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker 2023-09-02 12:56:36 -07:00
David Harris
1642ad2bad Improved NAPOT test coverage 2023-08-30 21:04:36 -07:00
Ross Thompson
310b700550 Have a working 32 bit cbom test! 2023-08-21 13:46:09 -05:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
af0e33209f Removed QEMU from configurations. 2023-07-19 10:23:55 -05:00
Ross Thompson
9533dee300 Got xcelium running wally, but it fails to actually preload the memories. 2023-07-12 13:56:57 -05:00
Ross Thompson
625192d9a4 Merge branch 'main' of github.com:ross144/cvw into main 2023-07-11 15:08:26 -05:00
Ross Thompson
27f6f00402 Changes for xcelium. 2023-07-07 18:22:28 -05:00
Ross Thompson
235546fa06 Merge branch 'main' of github.com:ross144/cvw 2023-07-07 13:25:00 -05:00
James E. Stine
67fdeae9c9 Add reset to wave window 2023-06-29 08:47:16 -05:00
Ross Thompson
c6a55c446a Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-27 11:04:27 -05:00
Ross Thompson
cc5d8fbf06 Updates for fpga. 2023-06-27 11:04:20 -05:00
James E. Stine
dd6b12c6dc Add signals for ResMatch & CheckNow to sim window that are related to TestFloat operation 2023-06-26 10:15:46 -05:00
James E. Stine
0b7b28c2f0 For some reason this was modified - I probably made a mistake - put back vsim 2023-06-22 15:26:22 -05:00
James E. Stine
1f63e6d483 Remove path for cvw.sv so its found 2023-06-22 15:25:56 -05:00
James E. Stine
66643eb78e Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file 2023-06-20 17:26:54 -05:00
eroom1966
5f358d1af7 add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
Ross Thompson
4428babda9 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
d2219023c3 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
David Harris
72002625eb Fixed cvw path in lint-wally 2023-06-15 07:02:59 -07:00
David Harris
430537a052 Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this. 2023-06-14 09:44:52 -07:00
Ross Thompson
311c00bb15 Updates to wave file. 2023-06-14 10:49:09 -05:00
David Harris
004aeda362 Revert "Update for new layout of ImperasDV files" 2023-06-13 04:17:56 -07:00
Ross Thompson
fe72264de3 The new testbench is almost working except the shadow copy is not working. 2023-06-12 15:08:23 -05:00
Ross Thompson
3ef2031791 Created temporary wrapper for lint. 2023-06-12 11:49:51 -05:00
eroom1966
d61ed17730 Update for new layout of ImperasDV files 2023-06-12 09:29:07 +01:00
Ross Thompson
e27dfb8ce0 Merge branch 'verilator' 2023-06-11 15:28:04 -05:00
James E. Stine
842f51dfeb Add notes for FP SoftFloat/TestFloat build as may be vague for some 2023-06-11 15:14:02 -05:00
David Harris
c9ca5108b1 Merge pull request #312 from ross144/main 
Fixed typo in coremark makefile.
 2023-06-06 05:44:22 -07:00
Ross Thompson
1ceea51d8b Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00
Ross Thompson
76fd76c155 Oups forgot to include updates to the lint script itself. 2023-05-31 11:00:38 -05:00
David Harris
df57ccd885 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-05-30 13:53:28 -07:00
Ross Thompson
8648d0c25c Hacked it together, but I think testfloat is working. 2023-05-30 15:51:13 -05:00
David Harris
51d001889a Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-05-30 13:40:56 -07:00
Ross Thompson
09aa460ed8 Updated do files for parameterization. 2023-05-30 15:38:03 -05:00
David Harris
fc1c4b710c Exclusions for decoders with new parameterization 2023-05-30 01:04:39 -07:00
David Harris
cc157463d5 Eliminated merging non-existent coverage 2023-05-30 00:38:30 -07:00
Ross Thompson
04d0fd94f0 Merge branch 'param-lim-merge' 2023-05-26 16:25:35 -05:00
Ross Thompson
b91b54589e Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down. 2023-05-24 14:05:44 -05:00
Ross Thompson
88cc473c68 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-24 13:00:50 -05:00
Ross Thompson
930fb67308 Trying to figure out why the parameterization slowed down modelsim so much. 2023-05-24 12:44:42 -05:00
David Harris
59020e6ef6 Removed unnecessary imperas tests from coverage 2023-05-23 15:43:11 -07:00
David Harris
8b69400034 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-05-22 11:27:57 -07:00
David Harris
21569b0a3b Verilate start 2023-05-22 10:30:39 -07:00
Ross Thompson
664231c0da Merge branch 'localhistory' 
Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
 2023-05-22 10:13:31 -05:00
Ross Thompson
429875e8db Repaired wave file. 2023-05-22 10:09:33 -05:00
Ross Thompson
bfd0d263ca Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-22 10:06:42 -05:00
Ross Thompson
ad3ecd35f0 Repaired wave file. 2023-05-22 09:50:34 -05:00
David Harris
7b0d1a7883 Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim 2023-05-16 11:37:01 -07:00
Ross Thompson
d545a2ec74 Partially working local history repair. 2023-05-11 14:56:26 -05:00
Ross Thompson
8b0791b6b5 I think ahead pipelining is working for local history. 2023-05-03 12:52:32 -05:00
David Harris
3d3b3a7432 Fixed IROM coverage issues in IFU 2023-05-01 08:32:52 -07:00
David Harris
d5b718be38 IMMU exclude non word-sized accesses 2023-05-01 08:14:19 -07:00
David Harris
6253c042b2 Merged coverage exclusions for PMP 2023-04-28 08:04:25 -07:00
David Harris
194b848fbf PMA Checker coverage 2023-04-28 07:53:59 -07:00
Liam
4d8eafd27d Pmpadrdecs test cases changing AdrMode to 2 or 3 
Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
 2023-04-27 12:23:35 -07:00
David Harris
a0e473b2e6 Merge pull request #282 from ross144/main 
Arty A7 board support, ImperasDV linux boot, CVW_v0.9 tag
 2023-04-27 07:23:10 -07:00
David Harris
ea3e3a1469 Merge pull request #283 from SydRiley/main 
Resolving unpackinput coverage issue with BadNaNBox, and increasing ifu and lsu coverage% through exclusions
 2023-04-26 15:40:01 -07:00
Sydeny
6415a5f0b2 For ifu and lsu exclusions added missing row numbers 2023-04-26 15:30:22 -07:00
Ross Thompson
212fee3613 Modified the imperas linux scripts so they run without reporting hundreds of gigabytes of data. 2023-04-26 17:29:57 -05:00
Sydeny
f49acd1293 Exclusion in the ifu and lsu to increase coverage, added missing row numbers 2023-04-26 15:26:39 -07:00
Sydeny
1a04ffcca9 Excluding untoggled signals in ifu and lsu, ifu coverage from 83.68% to 84.06% and lsu from 93.45% to 93.58% 2023-04-26 14:37:55 -07:00
Sydeny
cda71bea3f Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-26 03:00:25 -07:00
Sydeny
e5b3172cc9 added comments to exclusions 2023-04-26 03:00:13 -07:00
Alec Vercruysse
5612f30029 Cacheway Exclude FlushStage=1 when SetValidWay=1 
We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).

My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
 2023-04-25 20:30:46 -07:00
Alec Vercruysse
c19ed1990f extend invalidatecache d$ exclusion to statement coverage 2023-04-25 17:00:13 -07:00
Diego Herrera Vicioso
d29dc30288 Excluded coverage for impossible cases in wficountreg and status.MPRV 2023-04-24 02:06:53 -07:00
David Harris
086556310c Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage. 2023-04-22 12:22:45 -07:00
Ross Thompson
faac8d439a Merge pull request #264 from davidharrishmc/dev 
Added -fp flag to run arch64d/f tests in coverage
 2023-04-20 09:26:16 -05:00
David Harris
3a8d2db194 Merge pull request #262 from SydRiley/main 
removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
 2023-04-19 14:49:50 -07:00
Sydeny
ec730a7230 clarifying comments in exclusions 2023-04-19 14:47:34 -07:00
Sydeny
a132ffa7f7 removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98% 2023-04-19 13:30:12 -07:00
David Harris
ea9639435e Added -fp flag to run arch64d/f tests in coverage 2023-04-19 13:07:07 -07:00
Alec Vercruysse
de93bd6937 D$ scope-specific coverage exclusions (I$ logic that never fires) 
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.

Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.

There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
9ef85c547b fix unhit exclusion in fdivsqrtfsm 2023-04-19 01:34:01 -07:00
Sydeny
40853f4dc7 increasing lsu coverage by excluding the pmachecher/adrdecs/clintdec or uncoreram signal SizeValid becauseany size is valid so signal is always 1 2023-04-17 14:19:48 -07:00
David Harris
64fe318cb0 merged coverage exclusions 2023-04-17 10:17:48 -07:00
Ross Thompson
30e3d2cdce Merge pull request #233 from AlecVercruysse/coverage3 
Full I$ coverage
 2023-04-14 22:15:11 -05:00
Alec Vercruysse
4d9aa72877 replace instances of code duplication for i$ exclusions w/commands 2023-04-14 17:10:39 -07:00
David Harris
48de682ea8 Merged coverage-exclusions 2023-04-13 18:15:23 -07:00
David Harris
21db7a0d68 fdivsqrtfsm coverage attempt to waive a state 2023-04-13 17:40:14 -07:00
David Harris
5066cd99ab Merge pull request #237 from SydRiley/main 
fctrl coverage at 100% after removing redundancies from conditionals
 2023-04-13 17:10:46 -07:00
Limnanthes Serafini
1d72e56fec Merge branch 'openhwgroup:main' into cachesim 2023-04-13 16:54:35 -07:00
Limnanthes Serafini
95586abe09 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
034c289a36 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Sydeny
2b8891cefd Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu. 2023-04-13 16:27:53 -07:00
Alec Vercruysse
680aee7e07 Merge branch 'main' into coverage3 2023-04-12 16:00:15 -07:00
Alec Vercruysse
ad0e366766 track GetLinenum.do (tcl procedure to find line numbers to exclude) 2023-04-12 15:58:38 -07:00
Alec Vercruysse
01f2417524 cachefsm exclude icache logic without code reuse 2023-04-12 15:57:45 -07:00
James E. Stine
001a364d6c Modification to testfloat.do to accept argument for nowave or by default none 2023-04-12 14:49:40 -05:00
Ross Thompson
10be07857c Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
Alec Vercruysse
1cb6e1751b Merge branch 'main' into coverage3 2023-04-12 09:34:09 -07:00
Limnanthes Serafini
3f9a22e8d4 Minor comments. 2023-04-12 02:57:42 -07:00
David Harris
e6cb928ab2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-12 02:57:33 -07:00
Limnanthes Serafini
095f3d5542 Added performance and distribution to sim and wrapper. Added colors too! 2023-04-12 02:54:05 -07:00
Limnanthes Serafini
65d29306ef Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Alec Vercruysse
4cbb9bcec6 refactor cachefsm to get full coverage 
I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
 2023-04-12 01:15:35 -07:00
James Stine
744e170be3 Add feature in testfloat.do to elect wave or nowave 2023-04-11 22:35:04 -05:00