Rose Thompson
df88939bcb
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-24 13:14:25 -05:00
Rose Thompson
d0a5b278b7
Factored out the rvvi testbench code into rvvitbwrapper.
2024-07-24 13:10:57 -05:00
Rose Thompson
b1a711ae0f
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Rose Thompson
27f89fcdbd
Updated verilog-ethernet to remove all verilator warnings or at least suppress them.
2024-07-24 10:13:03 -05:00
Rose Thompson
9404a339ee
Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.
2024-07-23 17:44:37 -05:00
Rose Thompson
6c212ebf0e
Changes are confirmed to work on the FPGA.
2024-07-23 17:39:38 -05:00
Rose Thompson
e8e71ad643
Code cleanup.
2024-07-23 16:35:05 -05:00
Rose Thompson
57ea39d685
Fixed rvvi csr counting.
2024-07-23 16:22:23 -05:00
Rose Thompson
54e0289608
Fixed bugs in the rvvi synth logic which encoded csr instructions.
2024-07-23 16:16:11 -05:00
Rose Thompson
1eff86b7ae
Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
2024-07-23 13:18:03 -05:00
Rose Thompson
c463201d68
Moved all rvvi files to rvvi directory.
2024-07-23 13:03:21 -05:00
Rose Thompson
825dbefcb2
Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.
2024-07-23 12:26:03 -05:00
Rose Thompson
bb74a0f96b
Resolved more lint errors in the rvvi synthesized hardware.
2024-07-23 12:23:04 -05:00
Rose Thompson
42f2469ea7
Merge pull request #891 from davidharrishmc/dev
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Increased covergen.py functional coverage to 87.6%
2024-07-23 09:34:13 -05:00
David Harris
a4a0a10879
Increased covergen.py functional coverage to 87.6%
2024-07-23 04:38:13 -07:00
Rose Thompson
94a1ce32e7
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 17:48:34 -05:00
Rose Thompson
8ca565ed53
Updated for a better ILA rvvi debugger.
2024-07-22 17:44:04 -05:00
Rose Thompson
121342f4cc
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
2024-07-22 16:12:06 -05:00
Rose Thompson
00c30239bf
Cleaned up rvvisynth.sv
2024-07-22 12:22:41 -05:00
Rose Thompson
556c210e76
Added option to use rvvi ila
2024-07-22 12:19:37 -05:00
Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
32903a38f5
Merge pull request #890 from davidharrishmc/dev
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Fixed argument name in regression-wally
2024-07-22 12:00:25 -05:00
David Harris
4c46315907
Fixed argument name in regression-wally
2024-07-22 09:19:56 -07:00
Rose Thompson
844bc01c0a
Merge pull request #889 from davidharrishmc/dev
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Functional coverage improvements, fix WARL bug on MTVEC/STVEC
2024-07-22 10:59:16 -05:00
David Harris
040b359813
Added more RV64I coverage generation
2024-07-22 08:52:19 -07:00
Rose Thompson
24609f0b7f
Now have configurations to switch between supporting RVVI over ethernet.
2024-07-22 10:51:13 -05:00
David Harris
757cc8a5f7
Added QuestaFunctCoverage to merge functional coverage reports
2024-07-22 08:49:54 -07:00
David Harris
c4400dfeb0
Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode
2024-07-22 08:45:08 -07:00
Rose Thompson
d9ef588324
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 10:01:33 -05:00
David Harris
e949c9cfba
Removed more obsolete imperas scripts
2024-07-21 19:47:23 -07:00
David Harris
da502d2d5a
Fixed makefile log typo
2024-07-21 19:47:00 -07:00
David Harris
af79fd5702
Fixed hazard and rd_maxval coverage generation
2024-07-21 19:46:30 -07:00
David Harris
7fd8c6e29a
Removed outdated wally-imperas files
2024-07-21 19:45:22 -07:00
Jordan Carlin
5687e31c15
Merge pull request #888 from davidharrishmc/dev
2024-07-21 12:04:29 -07:00
David Harris
f30cc46ec5
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
2024-07-21 08:26:07 -07:00
Rose Thompson
00840e4893
Made the fpga top level configurable between rvvi synth and not.
2024-07-19 17:35:30 -05:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933
Cleanup in prep to merge the rvvi branch into main.
2024-07-19 15:48:20 -05:00
Rose Thompson
ce2cc48642
Updated verilog-ethernet to be compatible with wally.
2024-07-19 13:36:26 -05:00
Rose Thompson
a324e79b6f
Updated the ethernet frame gap for a faster computer.
2024-07-19 13:12:13 -05:00
Rose Thompson
9c1779a2d5
Added some documenation about sparse-checkout for verilog-ethernet submodule.
2024-07-19 13:11:48 -05:00
Rose Thompson
e751fbe865
Merge pull request #887 from davidharrishmc/dev
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Fully decode decompressed instructions, including hints and illegal registers/immediates
2024-07-19 09:23:36 -05:00
David Harris
c64c12dc6c
Detect illegal compressed immediates, hints
2024-07-18 22:48:32 -07:00
David Harris
945722cd5b
Neatly formatted decompress.sv
2024-07-18 22:01:43 -07:00
David Harris
ebea314a6e
Modified decompressor to look for illegal x0 values and hints
2024-07-18 21:38:17 -07:00
Rose Thompson
79d0cb96c2
Added verilog-ethernet as a submodule. Hoping we can make use of sparse-checkout as there are so many files in this repo.
2024-07-18 18:22:26 -05:00
David Harris
3b4726ea99
Check legal compressed nonzero destination registers, add c.nop decoding
2024-07-18 09:30:16 -07:00
David Harris
df063acf61
Refactored decompression to use simpler default illegal instruction
2024-07-18 08:26:58 -07:00
Rose Thompson
2fa7c49d5e
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-18 09:38:20 -05:00
David Harris
4d36072f09
Converted regression-wally to use argparse
2024-07-17 06:04:21 -07:00
