Removed outdated wally-imperas files

2025-02-11 06:05:49 +00:00 · 2024-07-21 19:45:22 -07:00 · 2024-07-21 19:45:22 -07:00 · 7fd8c6e29a
commit 7fd8c6e29a
parent f30cc46ec5
4 changed files with 0 additions and 224 deletions
--- a/sim/questa/sim-imperas
+++ b/sim/questa/sim-imperas
@ -1,33 +0,0 @@
-#!/bin/bash
-
-###########################################
-## imperas-one-time.sh
-##
-## Written: Ross Thompson (ross1728@gmail.com) and Lee Moore (moore@imperas.com)
-## Created: 31 January 2023
-## Modified: 31 January 2023
-##
-## Purpose: Run wally with imperas
-## 
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-## 
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https://solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-IMPERAS_TOOLS=$(pwd)/imperas.ic \
-OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
-TESTDIR=${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/Lee.S/  \
-vsim  -do "do wally-imperas.do rv64gc"
--- a/sim/questa/wally-imperas-cov.do
+++ b/sim/questa/wally-imperas-cov.do
@ -1,79 +0,0 @@
-# wally.do 
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-#
-# Modification by Oklahoma State University & Harvey Mudd College
-# Use with Testbench 
-# James Stine, 2008; David Harris 2021
-# Go Cowboys!!!!!!
-#
-# Takes 1:10 to run RV64IC tests using gui
-
-onbreak {resume}
-
-# create library
-if [file exists work] {
-    vdel -all
-}
-vlib work
-
-# compile source files
-# suppress spurious warnngs about 
-# "Extra checking for conflicts with always_comb done at vopt time"
-# because vsim will run vopt
-
-# start and run simulation
-# remove +acc flag for faster sim during regressions if there is no need to access internal signals
-        # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN.  For now just live with the warnings.
-vlog +incdir+$env(WALLY)/config/$1 \
-     +incdir+$env(WALLY)/config/deriv/$1 \
-     +incdir+$env(WALLY)/config/shared \
-     +define+USE_IMPERAS_DV \
-     +define+IDV_INCLUDE_TRACE2COV \
-     +define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \
-       +define+COVER_RV64I \
-       +define+COVER_RV64M \
-       +define+COVER_RV64A \
-       +define+COVER_RV64F \
-       +define+COVER_RV64D \
-       +define+COVER_RV64ZICSR \
-       +define+COVER_RV64C \
-     +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
-     +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
-     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv    \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
-     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv      \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv   \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv  \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv  \
-     \
-     +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv  \
-    \
-     $env(WALLY)/src/cvw.sv \
-     $env(WALLY)/testbench/testbench.sv \
-     $env(WALLY)/testbench/common/*.sv   \
-     $env(WALLY)/src/*/*.sv \
-     $env(WALLY)/src/*/*/*.sv \
-     -suppress 2583 \
-     -suppress 7063  \
-     +acc
-vopt +acc work.testbench -G DEBUG=1 -o workopt 
-eval vsim workopt +nowarn3829  -fatal 7 \
-     -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
-     +ElfFile=$env(TESTDIR)/ref/ref.elf $env(OTHERFLAGS) +TRACE2COV_ENABLE=1
-
-coverage save -onexit $env(WALLY)/sim/questa/riscv.ucdb
-
-
-view wave
-#-- display input and output signals as hexidecimal values
-# add log -recursive /*
-# do wave.do
-
-run -all
-
-noview $env(WALLY)/testbench/testbench-imperas.sv
-view wave
-
-#quit -f
--- a/sim/questa/wally-imperas-no-idv.do
+++ b/sim/questa/wally-imperas-no-idv.do
@ -1,48 +0,0 @@
-# wally.do 
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-#
-# Modification by Oklahoma State University & Harvey Mudd College
-# Use with Testbench 
-# James Stine, 2008; David Harris 2021
-# Go Cowboys!!!!!!
-#
-# Takes 1:10 to run RV64IC tests using gui
-
-onbreak {resume}
-
-# create library
-if [file exists work] {
-    vdel -all
-}
-vlib work
-
-# compile source files
-# suppress spurious warnngs about 
-# "Extra checking for conflicts with always_comb done at vopt time"
-# because vsim will run vopt
-
-# start and run simulation
-# remove +acc flag for faster sim during regressions if there is no need to access internal signals
-        # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN.  For now just live with the warnings.
-vlog +incdir+../config/$1 \
-     +incdir+../config/shared \
-     ../../external/ImperasDV-HMC/Imperas/ImpPublic/source/host/rvvi/rvviTrace.sv \
-     ../src/cvw.sv \
-     ../testbench/testbench_imperas.sv \
-     ../testbench/common/*.sv   \
-     ../src/*/*.sv \
-     ../src/*/*/*.sv \
-     -suppress 2583 \
-     -suppress 7063 
-vopt +acc work.testbench -G DEBUG=1 -o workopt 
-eval vsim workopt +nowarn3829  -fatal 7 \
-     +testDir=$env(TESTDIR) $env(OTHERFLAGS)
-view wave
-#-- display input and output signals as hexidecimal values
-add log -recursive /*
-do wave.do
-
-run -all
-
-noview ../testbench/testbench_imperas.sv
-view wave
--- a/sim/questa/wally-imperas.do
+++ b/sim/questa/wally-imperas.do
@ -1,64 +0,0 @@
-# wally.do 
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-#
-# Modification by Oklahoma State University & Harvey Mudd College
-# Use with Testbench 
-# James Stine, 2008; David Harris 2021
-# Go Cowboys!!!!!!
-#
-# Takes 1:10 to run RV64IC tests using gui
-
-onbreak {resume}
-
-# create library
-if [file exists work] {
-    vdel -all
-}
-vlib work
-
-# compile source files
-# suppress spurious warnngs about 
-# "Extra checking for conflicts with always_comb done at vopt time"
-# because vsim will run vopt
-
-# start and run simulation
-# remove +acc flag for faster sim during regressions if there is no need to access internal signals
-        # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN.  For now just live with the warnings.
-
-vlog +incdir+../config/$1 \
-     +incdir+../config/shared \
-     +define+USE_IMPERAS_DV \
-     +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
-     +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
-     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv    \
-     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv      \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv  \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv   \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv  \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv  \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv  \
-     $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv  \
-     ../src/cvw.sv \
-     ../testbench/testbench-imperas.sv \
-     ../testbench/common/*.sv   \
-     ../src/*/*.sv \
-     ../src/*/*/*.sv \
-     -suppress 2583 \
-     -suppress 7063 
-
-vopt +acc work.testbench -G DEBUG=1 -o workopt 
-eval vsim workopt +nowarn3829  -fatal 7 \
-     -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
-     +testDir=$env(TESTDIR) $env(OTHERFLAGS)
-view wave
-#-- display input and output signals as hexidecimal values
-add log -recursive /*
-do wave.do
-
-run -all
-
-noview ../testbench/testbench_imperas.sv
-view wave
-
-#quit -f