mirror of
https://github.com/openhwgroup/cvw
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Merge pull request #887 from davidharrishmc/dev
Fully decode decompressed instructions, including hints and illegal registers/immediates
This commit is contained in:
Rose Thompson
GitHub
commit
e751fbe865
@ -11,6 +11,7 @@
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#
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##################################
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import sys,os,shutil
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import argparse
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import multiprocessing
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from collections import namedtuple
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from multiprocessing import Pool, TimeoutError
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@ -320,13 +321,16 @@ coveragesim = "questa" # Questa is required for code/functional coverage
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#defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
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defaultsim = "verilator" # Default simulator for all other tests
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ccov = '--ccov' in sys.argv
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fp = '--fp' in sys.argv
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nightly = '--nightly' in sys.argv
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testfloat = '--testfloat' in sys.argv
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buildroot = '--buildroot' in sys.argv
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parser = argparse.ArgumentParser()
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parser.add_argument("--ccov", help="Code Coverage", action="store_true")
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parser.add_argument("--fcov", help="Functional Coverage", action="store_true")
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parser.add_argument("--nightly", help="Run large nightly regression", action="store_true")
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parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true")
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parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true")
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parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true")
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args = parser.parse_args()
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if (nightly):
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if (args.nightly):
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nightMode = "--nightly";
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# sims = [defaultsim] # uncomment to use only the default simulator
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sims = ["questa", "verilator", "vcs"] # uncomment to exercise all simulators
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@ -334,7 +338,7 @@ else:
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nightMode = ""
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sims = [defaultsim]
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if (ccov): # only run RV64GC tests in coverage mode
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if (args.ccov): # only run RV64GC tests in coverage mode
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coverStr = '--ccov'
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else:
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coverStr = ''
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@ -353,24 +357,24 @@ configs = [
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# run full buildroot boot simulation (slow) if buildroot flag is set. Start it early to overlap with other tests
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if (buildroot):
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if (args.buildroot):
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# addTests(tests_buildrootboot, defaultsim) # non-lockstep with Verilator runs in about 2 hours
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addTests(tests_buildrootbootlockstep, "questa") # lockstep with Questa and ImperasDV runs overnight
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if (ccov): # only run RV64GC tests on Questa in code coverage mode
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if (args.ccov): # only run RV64GC tests on Questa in code coverage mode
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addTests(tests64gc_nofp, "questa")
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if (fp):
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if (args.fp):
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addTests(tests64gc_fp, "questa")
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else:
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for sim in sims:
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if (not (buildroot and sim == defaultsim)): # skip shot buildroot sim if running long one
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if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one
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addTests(tests_buildrootshort, sim)
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addTests(tests, sim)
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addTests(tests64gc_nofp, sim)
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addTests(tests64gc_fp, sim)
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# run derivative configurations and lockstep tests in nightly regression
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if (nightly):
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if (args.nightly):
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addTests(derivconfigtests, defaultsim)
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sim_log = WALLY + "/sim/questa/logs/lockstep_coverage.log"
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tc = TestCase(
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@ -391,9 +395,9 @@ if (nightly):
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configs.append(tc)
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# testfloat tests
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if (testfloat): # for testfloat alone, just run testfloat tests
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if (args.testfloat): # for testfloat alone, just run testfloat tests
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configs = []
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if (testfloat or nightly): # for nightly, run testfloat along with others
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if (args.testfloat or args.nightly): # for nightly, run testfloat along with others
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testfloatsim = "questa" # change to Verilator when Issue #707 about testfloat not running Verilator is resolved
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testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"]
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for config in testfloatconfigs:
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@ -458,7 +462,7 @@ if (testfloat or nightly): # for nightly, run testfloat along with others
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def main():
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"""Run the tests and count the failures"""
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global configs, ccov
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global configs, args
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os.chdir(regressionDir)
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dirs = ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]
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for d in dirs:
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@ -467,17 +471,12 @@ def main():
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os.mkdir(d)
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except:
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pass
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if '--makeTests' in sys.argv:
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os.chdir(regressionDir)
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os.system('./make-tests.sh | tee ./logs/make-tests.log')
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elif '--ccov' in sys.argv:
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if args.ccov:
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TIMEOUT_DUR = 20*60 # seconds
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os.system('rm -f questa/cov/*.ucdb')
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elif '--nightly' in sys.argv:
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elif args.nightly in sys.argv:
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TIMEOUT_DUR = 60*1440 # 1 day
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elif '--testfloat' in sys.argv:
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elif args.testfloat in sys.argv:
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TIMEOUT_DUR = 30*60 # seconds
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else:
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TIMEOUT_DUR = 10*60 # seconds
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@ -497,7 +496,7 @@ def main():
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print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR))
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# Coverage report
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if ccov:
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if args.ccov:
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os.system('make QuestaCodeCoverage')
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# Count the number of failures
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if num_fail:
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2
bin/wsim
2
bin/wsim
@ -27,7 +27,7 @@ parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilat
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parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
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parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
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parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
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parser.add_argument("--fcov", "-f", help="Functional Coverage", action="store_true")
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parser.add_argument("--fcov", "-f", help="Functional Coverage, implies lockstep", action="store_true")
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parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
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parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
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parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
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@ -32,13 +32,15 @@ module decompress import cvw::*; #(parameter cvw_t P) (
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output logic [31:0] InstrD, // Decompressed instruction
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output logic IllegalCompInstrD // Invalid decompressed instruction
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);
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logic [32:0] LInstrD; // decompressed instruction with illegal flag in [32]
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logic [15:0] instr16;
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logic [4:0] rds1, rs2, rs1p, rs2p, rds1p, rdp;
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logic [11:0] immCILSP, immCILSPD, immCSS, immCSSD, immCL, immCLD, immCI, immCS, immCSD, immCB, immCIASP, immCIW;
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logic [19:0] immCJ, immCILUI;
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logic [5:0] immSH;
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logic [1:0] op;
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logic LegalCompInstrD;
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// Extract op and register source/destination fields
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assign instr16 = InstrRawD[15:0]; // instruction is already aligned
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@ -62,10 +64,10 @@ module decompress import cvw::*; #(parameter cvw_t P) (
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assign immCJ = {instr16[12], instr16[8], instr16[10:9], instr16[6], instr16[7], instr16[2], instr16[11], instr16[5:3], {9{instr16[12]}}};
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assign immCB = {{4{instr16[12]}}, instr16[6:5], instr16[2], instr16[11:10], instr16[4:3], instr16[12]};
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assign immCI = {{7{instr16[12]}}, instr16[6:2]};
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assign immCILUI = {{15{instr16[12]}}, instr16[6:2]};
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assign immCIASP = {{3{instr16[12]}}, instr16[4:3], instr16[5], instr16[2], instr16[6], 4'b0000};
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assign immCILUI = {{15{instr16[12]}}, instr16[6:2]}; // c.lui
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assign immCIASP = {{3{instr16[12]}}, instr16[4:3], instr16[5], instr16[2], instr16[6], 4'b0000}; // c.addi16sp
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assign immCIW = {2'b00, instr16[10:7], instr16[12:11], instr16[5], instr16[6], 2'b00};
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assign immSH = {instr16[12], instr16[6:2]};
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assign immSH = {instr16[12], instr16[6:2]}; // c. shift instructions: c.srli, c.srai, c.slli
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// only for RV128
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// assign immCILSPQ = {2{instr16[5]}, instr16[5:2], instr16[12], instr16[6], 4'b0000};
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@ -75,173 +77,110 @@ module decompress import cvw::*; #(parameter cvw_t P) (
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always_comb
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if (op == 2'b11) begin // noncompressed instruction
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InstrD = InstrRawD;
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IllegalCompInstrD = '0;
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LInstrD = {1'b1, InstrRawD};
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end else begin // convert compressed instruction into uncompressed
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IllegalCompInstrD = '0;
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LInstrD = {1'b0, 16'b0, instr16}; // if a legal instruction is not decoded, default to illegal and preserve 16-bit value for mtval
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case ({op, instr16[15:13]})
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5'b00000: if (immCIW != 0) InstrD = {immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn
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else begin // illegal instruction
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IllegalCompInstrD = 1'b1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b00001: if (P.ZCD_SUPPORTED)
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InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
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else begin // unsupported instruction
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IllegalCompInstrD = 1'b1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
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5'b00011: if (P.XLEN==32)
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if (P.ZCF_SUPPORTED)
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InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
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else begin
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IllegalCompInstrD = 1'b1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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else
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InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
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5'b00000: if (immCIW != 0) LInstrD = {1'b1, immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn
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5'b00001: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
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5'b00010: LInstrD = {1'b1, immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
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5'b00011: if (P.XLEN==32) begin
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if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
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end else LInstrD = {1'b1, immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld
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5'b00100: if (P.ZCB_SUPPORTED)
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if (instr16[12:10] == 3'b000)
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InstrD = {10'b0, instr16[5], instr16[6], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu
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if (instr16[12:10] == 3'b000) LInstrD = {1'b1, 10'b0, instr16[5], instr16[6], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu
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else if (instr16[12:10] == 3'b001) begin
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if (instr16[6])
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InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh
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else
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InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu
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if (instr16[6]) LInstrD = {1'b1, 10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh
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else LInstrD = {1'b1, 10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu
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end else if (instr16[12:10] == 3'b010)
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InstrD = {7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[5], instr16[6], 7'b0100011}; // c.sb
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LInstrD = {1'b1, 7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[5], instr16[6], 7'b0100011}; // c.sb
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else if (instr16[12:10] == 3'b011 & instr16[6] == 1'b0)
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InstrD = {7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0100011}; // c.sh
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else begin
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IllegalCompInstrD = 1'b1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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else begin
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IllegalCompInstrD = 1'b1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b00101: if (P.ZCD_SUPPORTED)
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InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
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else begin // unsupported instruction
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IllegalCompInstrD = 1'b1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
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5'b00111: if (P.XLEN==32)
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if (P.ZCF_SUPPORTED)
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InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
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else begin
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IllegalCompInstrD = 1'b1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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else
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InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd
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5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
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5'b01001: if (P.XLEN==32)
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InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal
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else
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InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
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5'b01010: InstrD = {immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li
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5'b01011: if (rds1 != 5'b00010)
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InstrD = {immCILUI, rds1, 7'b0110111}; // c.lui
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else
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InstrD = {immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp
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5'b01100: if (instr16[11:10] == 2'b00)
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InstrD = {6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli
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else if (instr16[11:10] == 2'b01)
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InstrD = {6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai
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else if (instr16[11:10] == 2'b10)
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InstrD = {immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi
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else if (instr16[12:10] == 3'b011)
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if (instr16[6:5] == 2'b00)
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InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.sub
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else if (instr16[6:5] == 2'b01)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011}; // c.xor
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else if (instr16[6:5] == 2'b10)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
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else // if (instr16[6:5] == 2'b11)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
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else begin // (instr16[12:10] == 3'b111)
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LInstrD = {1'b1, 7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0100011}; // c.sh
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5'b00101: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
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5'b00110: LInstrD = {1'b1, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
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5'b00111: if (P.XLEN==32) begin
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if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
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end else LInstrD = {1'b1, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; // c.sd
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5'b01000: if (rds1 != 5'b0)
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if (immCI[5:0] != 0) LInstrD = {1'b1, immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
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else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.addi with imm = 0 is a HINT, treated as nop
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else if (immCI[5:0] == 6'b0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.nop = addi x0, x0, 0
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else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.nop with imm != 0 is a HINT, treated as nop
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5'b01001: if (P.XLEN==32) LInstrD = {1'b1, immCJ, 5'b00001, 7'b1101111}; // c.jal
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else if (rds1 != 5'b0) LInstrD = {1'b1, immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
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5'b01010: if (rds1 != 5'b0) LInstrD = {1'b1, immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li
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else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.li with rd = 0 is a HINT, treated as nop
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5'b01011: if (rds1 == 5'b00010) begin
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if (immCIASP[9:4] != 6'b0) LInstrD = {1'b1, immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp
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end else if (immCILUI[5:0] != 0)
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if (rds1 != 5'b0) LInstrD = {1'b1, immCILUI, rds1, 7'b0110111}; // c.lui
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else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.lui with rd = 0, imm!=0 is a HINT, treated as nop
|
||||
5'b01100: if (instr16[11:10] == 2'b00) begin
|
||||
if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli; shamt[5] must be 0 in RV32C
|
||||
end else if (instr16[11:10] == 2'b01) begin
|
||||
if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai; shamt[5] must be 0 in RV32C
|
||||
end else if (instr16[11:10] == 2'b10) LInstrD = {1'b1, immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi
|
||||
else if (instr16[12:10] == 3'b011) begin
|
||||
if (instr16[6:5] == 2'b00) LInstrD = {1'b1, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.sub
|
||||
else if (instr16[6:5] == 2'b01) LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011}; // c.xor
|
||||
else if (instr16[6:5] == 2'b10) LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
|
||||
else LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
|
||||
end else begin // (instr16[12:10] == 3'b111)
|
||||
if (instr16[6:5] == 2'b00 & P.XLEN > 32)
|
||||
InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
|
||||
LInstrD = {1'b1, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
|
||||
else if (instr16[6:5] == 2'b01 & P.XLEN > 32)
|
||||
InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
|
||||
LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
|
||||
else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED)
|
||||
InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
|
||||
LInstrD = {1'b1, 12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
|
||||
else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED)
|
||||
InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
|
||||
LInstrD = {1'b1, 12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
|
||||
else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED)
|
||||
InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h
|
||||
LInstrD = {1'b1, 7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h
|
||||
else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED)
|
||||
InstrD = {12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h
|
||||
LInstrD = {1'b1, 12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h
|
||||
else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED)
|
||||
InstrD = {12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori
|
||||
LInstrD = {1'b1, 12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori
|
||||
else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.ZBA_SUPPORTED & P.XLEN > 32)
|
||||
InstrD = {7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0
|
||||
LInstrD = {1'b1, 7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0
|
||||
else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED & P.ZMMUL_SUPPORTED)
|
||||
InstrD = {7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul
|
||||
else begin // reserved
|
||||
IllegalCompInstrD = 1'b1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
/** end else begin // illegal instruction
|
||||
IllegalCompInstrD = 1'b1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap **/
|
||||
LInstrD = {1'b1, 7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul
|
||||
end
|
||||
5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
|
||||
5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
|
||||
5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
|
||||
5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
|
||||
5'b01101: LInstrD = {1'b1, immCJ, 5'b00000, 7'b1101111}; // c.j
|
||||
5'b01110: LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
|
||||
5'b01111: LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
|
||||
5'b10000: if (rds1 != 5'b0) begin
|
||||
if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli; shamt[5] must be 0 in RV32C
|
||||
end else if (immSH != 0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.slli with rd = 0, immm != 0 is a HINT, treated as nop
|
||||
5'b10001: if (P.ZCD_SUPPORTED)
|
||||
InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
|
||||
else begin // unsupported instruction
|
||||
IllegalCompInstrD = 1'b1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
|
||||
5'b10011: if (P.XLEN == 32)
|
||||
if (P.ZCF_SUPPORTED)
|
||||
InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
|
||||
else begin
|
||||
IllegalCompInstrD = 1'b1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
else
|
||||
InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
|
||||
if (rds1 != 5'b0) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
|
||||
5'b10010: if (rds1 != 5'b0) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
|
||||
5'b10011: if (P.XLEN == 32) begin
|
||||
if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
|
||||
end else if (rds1 != 5'b0) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
|
||||
5'b10100: if (instr16[12] == 0)
|
||||
if (instr16[6:2] == 5'b00000)
|
||||
InstrD = {7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr
|
||||
else
|
||||
InstrD = {7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv
|
||||
if (rs2 == 5'b00000) begin
|
||||
if (rds1 != 5'b0) LInstrD = {1'b1, 7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr
|
||||
end else
|
||||
if (rds1 != 5'b0) LInstrD = {1'b1, 7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv
|
||||
else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.mv with rd = 0 is a HINT, treated as nop
|
||||
else
|
||||
if (rs2 == 5'b00000)
|
||||
if (rds1 == 5'b00000)
|
||||
InstrD = {12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak
|
||||
else
|
||||
InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
|
||||
else
|
||||
InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
|
||||
5'b10101: if (P.ZCD_SUPPORTED)
|
||||
InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
|
||||
else begin // unsupported instruction
|
||||
IllegalCompInstrD = 1'b1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
|
||||
5'b10111: if (P.XLEN==32)
|
||||
if (P.ZCF_SUPPORTED)
|
||||
InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
|
||||
else begin
|
||||
IllegalCompInstrD = 1'b1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
else
|
||||
InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
|
||||
default: begin // illegal instruction
|
||||
IllegalCompInstrD = 1'b1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
if (rs2 == 5'b00000) begin
|
||||
if (rds1 == 5'b00000) LInstrD = {1'b1, 12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak
|
||||
else if (rds1 != 5'b0) LInstrD = {1'b1, 12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
|
||||
end else
|
||||
if (rds1 != 0) LInstrD = {1'b1, 7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
|
||||
else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.add with rd = 0 is a HINT, treated as nop, even if it is a C.NTL
|
||||
5'b10101: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
|
||||
5'b10110: LInstrD = {1'b1, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
|
||||
5'b10111: if (P.XLEN==32) begin
|
||||
if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
|
||||
end else LInstrD = {1'b1, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
|
||||
default: ; // illegal instruction
|
||||
endcase
|
||||
end
|
||||
|
||||
// extract instruction and illegal from LInstrD
|
||||
assign {LegalCompInstrD, InstrD} = LInstrD;
|
||||
assign IllegalCompInstrD = ~LegalCompInstrD;
|
||||
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user