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5,146 Commits 5 Branches 2 Tags 53 MiB
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137 Commits

Author SHA1 Message Date
Ross Thompson
6945eaf045 Fixed bug with the new csr. 2023-01-28 17:56:56 -06:00
Ross Thompson
684a7214cb Added another performance counter to track overall branch miss-predictions. 2023-01-28 17:50:46 -06:00
Ross Thompson
bbb47fc943 Changed the performance counters to track different data. 
Now rather than tracking jump(r) we track jump(r) and taken branches.
 2023-01-26 13:21:28 -06:00
Ross Thompson
07308e2c14 Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
David Harris
53d0d28828 csr cleanup 2023-01-13 22:12:06 -08:00
David Harris
b7f579a146 csr cleanup 2023-01-13 21:29:03 -08:00
David Harris
c5358da771 csr cleanup 2023-01-13 21:25:55 -08:00
David Harris
97bddf0d54 csr cleanup 2023-01-13 21:09:29 -08:00
David Harris
e4f4b31896 csr cleanup 2023-01-13 21:00:06 -08:00
David Harris
7358402bc0 csr cleanup 2023-01-13 20:55:21 -08:00
David Harris
9da2fae1f3 csr comments 2023-01-13 20:49:34 -08:00
David Harris
a9008cb293 trap comments 2023-01-13 19:50:44 -08:00
David Harris
370678f730 trap comments 2023-01-13 19:44:38 -08:00
David Harris
27f81b09ce privileged comments 2023-01-13 17:57:38 -08:00
Ross Thompson
4a73018d6e Merge branch 'rastemp' 2023-01-13 18:09:50 -06:00
Ross Thompson
8e3e8591a6 Removed 1 bit from instruction classification. 2023-01-13 15:19:53 -06:00
David Harris
496d343660 Privileged unit formatting 2023-01-12 07:41:30 -08:00
David Harris
a3a736091c Restructured negateintres to avoid lint error, but one still shows on shiftcorrection 2023-01-12 07:28:52 -08:00
David Harris
e67f125201 Header comments 2023-01-12 04:35:44 -08:00
David Harris
7d93659f6b changed name to CORE-V-WALLY 2023-01-11 15:15:08 -08:00
David Harris
b911056e66 Changed Wally to CORE-V Wally 2023-01-11 14:03:44 -08:00
David Harris
e92cffbb5e Changed MIT license to Solderpad License 2023-01-10 11:35:20 -08:00
David Harris
15b829bbf7 Removed unused signals 2023-01-07 06:06:54 -08:00
Ross Thompson
e34f80db2f More branch predictor cleanup. 2023-01-05 17:19:27 -06:00
Ross Thompson
8ca6c1255e More branch predictor cleanup. 2023-01-05 13:36:51 -06:00
Ross Thompson
b14b71c7a9 Fixed bug with the performance counters not updating. 2022-12-24 14:24:17 -06:00
Ross Thompson
b5a85b55f1 Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
David Harris
1f6dc62bb3 Moved InstrValidNotFLushed to csr including InstrValidM 2022-12-23 00:27:44 -08:00
David Harris
85d0b697bf Removed unused StallW from CSRs 2022-12-23 00:21:36 -08:00
David Harris
93bb8036be Revert to 98b824 2022-12-22 23:58:14 -08:00
David Harris
51b92285d3 Removed unused signals in FPU and CSR 2022-12-22 22:59:05 -08:00
David Harris
567f76c2a5 Code cleanup 2022-12-22 10:04:50 -08:00
David Harris
3562542728 comment cleanup 2022-12-21 12:39:09 -08:00
David Harris
ca949f2110 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
Ross Thompson
f6393d1288 Waiting on fix for wally64periph uart test. 
would like to remove vectored interrupt adder.
 2022-12-21 13:16:09 -06:00
Ross Thompson
c41d58bd29 Vectored interrupts now require 64 byte alignment. 
Eliminates adder.
 2022-12-21 12:05:49 -06:00
David Harris
28085ce8eb Clean up vecgtored interrupts 2022-12-20 16:53:09 -08:00
David Harris
88ee834c97 Converted tvecmux to structural 2022-12-20 16:24:04 -08:00
Ross Thompson
2f0d20b8b0 privileged pc mux cleanup. 2022-12-20 18:05:44 -06:00
Ross Thompson
cba2ed64e5 Moved privileged pc logic into privileged unit. 2022-12-20 17:55:45 -06:00
Ross Thompson
ef4ecbe62b Changed long names of vectored pcm signals. 2022-12-20 17:01:20 -06:00
David Harris
0c10ec942a Replaced || and && with single ops 2022-12-20 01:33:35 -08:00
David Harris
940fd2f924 Clean up interrupt masking by Commit 2022-12-16 08:27:39 -08:00
Ross Thompson
fbf543bf57 Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault. 2022-11-29 17:19:31 -06:00
Ross Thompson
0ed0c18aa1 Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered. 2022-10-02 16:21:21 -05:00
Ross Thompson
32449dfe97 Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache. 2022-09-28 17:39:51 -05:00
David Harris
05aa18fe14 Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
David Harris
129fab3794 Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
David Harris
31815422d2 ../src/privileged/csrc.sv 2022-05-31 21:12:17 +00:00
David Harris
2935188035 Moved delegation logic from privmode to trap to simplify interface 2022-05-31 14:58:11 +00:00