Ross Thompson
91e64a0d67
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
f04ca5cb6a
Fixed regression-wally to correct remove and mkdir wkdir.
2022-12-16 12:51:21 -06:00
David Harris
a8126458f6
Refactored stalls and flushes, including FDIV flush with FlushE
2022-12-15 10:56:18 -08:00
David Harris
97a432570a
Regression delete wkdir files to prevent spurious failures
2022-12-15 10:24:58 -08:00
David Harris
3a8602523e
FPU test list
2022-12-01 10:18:36 -08:00
Ross Thompson
fa22484cfe
Reverted the IROM/DTIM address range modelsim assignment.
2022-11-30 17:13:33 -06:00
Ross Thompson
2f582cd91f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-30 13:30:37 -06:00
Ross Thompson
de538d1c2f
Intermediate commit. Replaced flip flop dirty bit array with sram.
2022-11-30 00:08:31 -06:00
cturek
10c2d45888
div tests in sim-wally
2022-11-30 02:32:04 +00:00
Ross Thompson
fbf543bf57
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
96cc4c7ebe
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
78acd40424
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
6dd5668d21
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-22 18:07:32 -06:00
cturek
78c2ce5649
Updated testbench/wave for fdivsqrt new start signals
2022-11-22 22:22:26 +00:00
Ross Thompson
4e926ba4cf
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
13e6f7d80b
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
788ae5fb18
Updated wave file.
2022-11-13 21:34:45 -06:00
Ross Thompson
d912981ec9
Wavefile update.
2022-11-10 15:48:06 -06:00
Ross Thompson
51408c620e
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
d6f907f444
Sort of solved the bit width warning for dtim, irom ranges.
2022-10-19 10:42:19 -05:00
David Harris
aa5fe52407
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-14 17:33:36 -07:00
David Harris
51b702fa17
Removed unused FPU waves
2022-10-14 17:33:32 -07:00
Ross Thompson
22603464ae
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
dfd07a57fd
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
David Harris
cc9a2fc62d
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
David Harris
31e9af0eb2
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
Ross Thompson
9d23b0e6d6
Reorganized the configs.
2022-10-09 16:46:48 -05:00
Ross Thompson
b01ee070bd
Updated wavefile.
2022-10-05 14:55:40 -05:00
Kip Macsai-Goren
9a0b98037b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
fb464b9546
Renamed endianswap to match module name
2022-10-04 17:33:49 +00:00
Ross Thompson
2c0132aa9c
Renamed signals in EBU.
2022-09-29 18:29:38 -05:00
David Harris
46680b80a7
Eliminated store after store stall when no cache; simplified divshiftcalc logic.
2022-09-21 13:02:34 -07:00
Ross Thompson
ac864a6ca3
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
...
Fixed a major issue with the real SRAM implemenation.
2022-09-21 12:20:00 -05:00
David Harris
653c458241
Moved fpu modules into subdirectories
2022-09-20 04:12:05 -07:00
David Harris
59b6346a28
Removed unused otfc for Q
2022-09-19 00:43:27 -07:00
Ross Thompson
cea012a640
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
c7d3580637
Renamed signals in the LSU.
2022-09-13 11:47:39 -05:00
David Harris
c730ddf74a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 11:11:39 -07:00
David Harris
7a29f9c95b
Running 16-bit square root cases first in testfloat
2022-09-07 11:11:35 -07:00
Ross Thompson
0615798467
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 12:26:50 -05:00
Ross Thompson
83306ec238
Named change for ahb tests to be less annoying.
2022-09-07 12:24:41 -05:00
Ross Thompson
3571fb18c2
Modified regression tests to add some ahb configurations.
2022-09-07 12:03:58 -05:00
David Harris
dff9416a33
Added rv32i config for regression of wally32periph
2022-09-07 09:37:59 -07:00
Ross Thompson
5a0cda9860
Merge branch 'multimanager' into main
2022-09-07 10:54:27 -05:00
David Harris
19e449b83d
Fixed regression for divsqrt radix2
2022-09-07 06:12:23 -07:00
Ross Thompson
c87268baf1
Modified ram_ahb to work with different latencies.
2022-09-04 14:46:15 -05:00
David Harris
5e26bcced1
Fixed lint errors in square root and improved waveforms in testfloat
2022-09-01 15:49:13 -07:00
Ross Thompson
f2f1169a04
Renamed AHBCachebusdp to abhcacheinterface.
2022-08-31 14:12:19 -05:00
Ross Thompson
f3d611c686
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-31 11:38:29 -05:00
Ross Thompson
5409501ca6
Maybe fixed it?
2022-08-30 18:08:34 -05:00
Ross Thompson
cce3fdd0e3
Updates to wave file.
2022-08-30 17:34:36 -05:00
Ross Thompson
8b9f30c91a
more progress.
2022-08-30 17:32:32 -05:00
Ross Thompson
fab3a2b791
Temporary commit.
2022-08-30 15:40:42 -05:00
Ross Thompson
315f662eb9
More progress.
2022-08-30 15:27:19 -05:00
Ross Thompson
637d60b64c
Progress.
2022-08-30 14:17:00 -05:00
David Harris
e1760dde55
Fixed checking termination in testfloat testbench
2022-08-30 10:55:21 -07:00
David Harris
7d4e85bf21
Separated out radix 2 and radix 4 stages into different modules
2022-08-29 04:26:14 -07:00
David Harris
2788022c22
renamed srt to fdivsqrt
2022-08-29 04:04:05 -07:00
David Harris
f2517f8290
Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
2022-08-27 20:31:09 -07:00
David Harris
60b673cafd
Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus
2022-08-27 05:31:56 -07:00
David Harris
37f0b52520
Fixed address decoder hanging buildroot
2022-08-26 22:01:25 -07:00
Ross Thompson
3b612d6201
Possible fixes for earily messup of rv32ic and rv64ic configs.
2022-08-25 14:42:08 -05:00
Ross Thompson
b0aea77b20
Added generate around uncore.
2022-08-25 10:35:24 -05:00
Ross Thompson
01a7718471
Added generate around ebu.
2022-08-25 09:24:13 -05:00
Ross Thompson
d10edfa5e0
No longer need wally-pipelined-fpga.do.
2022-08-24 18:10:45 -05:00
Ross Thompson
fc22e807e2
Merged testbench-fpga into testbench.
...
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
2022-08-24 17:52:25 -05:00
Ross Thompson
517c0f6c35
Changed signal names.
2022-08-17 16:12:04 -05:00
Katherine Parry
cb0c1b7488
radix-2 1 copy passes testfloat
2022-08-06 22:54:05 +00:00
David Harris
7e5b78f240
plic-s debug
2022-08-03 12:33:09 +00:00
Ross Thompson
413a9bf58b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-01 22:09:11 -05:00
David Harris
257107f908
Partitioned fma into separate files
2022-08-01 18:07:38 +00:00
Ross Thompson
1ee613ae6c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-07-31 12:48:51 -05:00
David Harris
2d7f4b133c
More work toward riscof tests
2022-07-26 06:19:13 -07:00
David Harris
416f5edfe0
More riscof makefile tuning
2022-07-25 21:15:56 +00:00
David Harris
7f7b3359b0
Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings
2022-07-25 20:50:38 +00:00
Ross Thompson
719b00e338
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
2022-07-24 01:20:29 -05:00
Ross Thompson
69d520a7eb
Removed replay from the config files.
2022-07-24 00:34:11 -05:00
Ross Thompson
f3cf46d633
Added more i-cache signals to wave file.
2022-07-24 00:24:13 -05:00
Ross Thompson
8193946996
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-07-23 08:41:59 -05:00
Ross Thompson
abc79c6c8e
Possible improvement to cache which removes the cpu_busy states.
2022-07-22 23:20:37 -05:00
Daniel Torres
d0aaae26fe
fixed wally rv32e tests, updated regression makefile to new testflow
2022-07-22 17:09:46 -07:00
Katherine Parry
b3d932cd61
divider sizes reworked to match book
2022-07-22 22:02:04 +00:00
Katherine Parry
fbe8bb2298
radix-4 division integrated into srt - not tested
2022-07-21 19:38:06 +00:00
Ross Thompson
8698799077
Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
2022-07-19 22:42:25 -05:00
Ross Thompson
a79e5e11f6
Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
2022-07-18 23:37:18 -05:00
Katherine Parry
cce5fb8dfd
moved Ss to execute stage
2022-07-18 20:48:56 +00:00
Katherine Parry
7268b4b334
removed underflow from inexactct calculation
2022-07-18 17:51:18 +00:00
Katherine Parry
5cb9c9f319
merged floating-point radix-2 divider with radix-4
2022-07-15 20:16:59 +00:00
Katherine Parry
2fe8b6e34c
fixed error in divsqrt
2022-07-14 18:16:00 +00:00
Katherine Parry
3c1bea1104
removed warnings and took a mux out of the critical path
2022-07-12 18:32:17 -07:00
Katherine Parry
18d7fee541
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-07-12 22:37:20 +00:00
Katherine Parry
bea4ec078d
variable interations implemented in radix-4 divider
2022-07-11 18:30:21 -07:00
Katherine Parry
97e7e619d9
moved fpu ieu write data mux to lsu
2022-07-08 23:56:57 +00:00
Katherine Parry
75a8cea4e4
srt divider merged into fpu
2022-07-07 16:01:33 -07:00
slmnemo
261248538c
sim-buildroot-batch now runs wally-pipelined-batch
...
with option buildroot buildroot-no-trace to boot linux from step 0
2022-07-06 18:06:43 -07:00
David Harris
1bf701d958
Added check to halt testbench on failing to find file
2022-07-05 02:28:59 +00:00
slmnemo
39831e3a40
./regression-wally -buildroot or ./regression-wally -all now builds Linux from instruction 0 instead of trying to reach instruction 246000000
2022-06-29 13:40:11 -07:00
Katherine Parry
a5fb60eb1a
radix-4 early termination working for special cases - not working completely
2022-06-27 20:43:55 +00:00
Katherine Parry
43882d5878
modified result select to account for x/inf
2022-06-24 21:23:15 +00:00
Katherine Parry
b16e55906a
div debug - accounted for 1 bit normalization in exponent calculation
2022-06-23 22:59:43 +00:00
