cvw/pipelined/regression
2022-09-07 12:26:50 -05:00
..
slack-notifier
wave-dos Added generate around uncore. 2022-08-25 10:35:24 -05:00
wkdir
buildrootBugFinder.py
fpga-wave.do Added generate around uncore. 2022-08-25 10:35:24 -05:00
lint-wally
linux-wave.do Added generate around uncore. 2022-08-25 10:35:24 -05:00
make-tests.sh
Makefile
makefile-memfile
regression-wally Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 12:26:50 -05:00
sim-buildroot
sim-buildroot-batch
sim-testfloat
sim-testfloat-batch
sim-wally Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00
sim-wally-batch Fixed address decoder hanging buildroot 2022-08-26 22:01:25 -07:00
testfloat.do Fixed lint errors in square root and improved waveforms in testfloat 2022-09-01 15:49:13 -07:00
wally-harvard.do
wally-pipelined-batch.do Named change for ahb tests to be less annoying. 2022-09-07 12:24:41 -05:00
wally-pipelined.do Modified regression tests to add some ahb configurations. 2022-09-07 12:03:58 -05:00
wave-all.do Added generate around uncore. 2022-08-25 10:35:24 -05:00
wave-fpu.do Fixed lint errors in square root and improved waveforms in testfloat 2022-09-01 15:49:13 -07:00
wave.do Fixed regression for divsqrt radix2 2022-09-07 06:12:23 -07:00