cvw/pipelined/regression
2022-09-29 18:29:38 -05:00
..
slack-notifier
wave-dos
wkdir
buildrootBugFinder.py
fpga-wave.do Merged together bram1p1rw with sram1p1rw as sram1p1rw. 2022-09-21 12:20:00 -05:00
lint-wally
linux-wave.do Merged together bram1p1rw with sram1p1rw as sram1p1rw. 2022-09-21 12:20:00 -05:00
make-tests.sh
Makefile
makefile-memfile
regression-wally Eliminated store after store stall when no cache; simplified divshiftcalc logic. 2022-09-21 13:02:34 -07:00
sim-buildroot
sim-buildroot-batch
sim-testfloat Running 16-bit square root cases first in testfloat 2022-09-07 11:11:35 -07:00
sim-testfloat-batch
sim-wally Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00
sim-wally-batch Fixed address decoder hanging buildroot 2022-08-26 22:01:25 -07:00
testfloat.do Moved fpu modules into subdirectories 2022-09-20 04:12:05 -07:00
wally-harvard.do
wally-pipelined-batch.do Named change for ahb tests to be less annoying. 2022-09-07 12:24:41 -05:00
wally-pipelined.do Modified regression tests to add some ahb configurations. 2022-09-07 12:03:58 -05:00
wave-all.do
wave-fpu.do Removed unused otfc for Q 2022-09-19 00:43:27 -07:00
wave.do Renamed signals in EBU. 2022-09-29 18:29:38 -05:00