Jacob Pease
dcb2edf888
Fixed syntax bugs. inline functions are now static and in the spi.h header.
2024-07-23 17:00:32 -05:00
Jacob Pease
5f0addd69a
Initial pass on SPI based bootloader code finished.
2024-07-23 16:33:49 -05:00
Jacob Pease
a8b9e7776b
Added some minor error checking to gpt.c.
2024-07-23 16:32:52 -05:00
Jacob Pease
ab00ea5a5c
Added sd_read64 to help with block reads and crc checking.
2024-07-23 16:32:29 -05:00
Jacob Pease
57eeba5c8c
Progress made on implementing new disk read function.
2024-07-23 15:47:23 -05:00
Jacob Pease
9ccb0eb027
Removed references to card_type.
2024-07-23 15:46:18 -05:00
Jacob Pease
bf65cd2817
Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c
2024-07-23 14:18:42 -05:00
Jacob Pease
b05052311f
Added sd_cmd and utility SPI functions.
2024-07-22 16:57:04 -05:00
Jacob Pease
cec39fd3aa
Added new SDC clock constraint.
2024-07-22 13:05:16 -05:00
Jacob Pease
a506d76149
Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
2024-07-22 12:36:39 -05:00
Jacob Pease
e91d2c8b14
Corrected the CRC7 code with the right sequence of instructions.
2024-07-22 01:19:10 -05:00
Jacob Pease
c7d869bc96
Added inital spi based sd card code. Working on CRC7 code that works.
2024-07-20 14:00:43 -05:00
Jacob Pease
53b2a51c89
Added tentative spi_send_byte function.
2024-07-19 12:30:32 -05:00
Jacob Pease
34e89e842c
Added initial spi code to fpga/zsbl
2024-07-19 11:35:12 -05:00
Ross Thompson
ab1ee3d69b
Removed *** from IFU, lrcs.
2024-06-19 09:40:35 -07:00
Ross Thompson
c5dac4d775
Removed *** from fpga top.
2024-06-19 09:28:21 -07:00
Jacob Pease
7a417d7a6c
Added true bootloader to fpga/zsbl directory.
2024-05-31 15:28:25 -05:00
Jacob Pease
3f7659c8ad
Removed old fpgaTop.v file.
2024-05-30 16:15:19 -05:00
Jacob Pease
7ecd1c7d5f
The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
2024-05-30 15:48:27 -05:00
Rose Thompson
8123695831
Maded insert_debug_comment.sh compatible with cygwin.
2024-04-22 10:48:34 -05:00
Rose Thompson
3bed733301
Fixed fpga to work with the updated regression changes.
2024-04-22 10:42:01 -05:00
Rose Thompson
c1221e6608
Fixed insert_debug_comment.sh to work with the older version of bash.
2024-04-16 10:55:26 -05:00
Rose Thompson
6097444b5a
Added missing file for compiling the fpga zero stage bootloader.
2024-04-11 10:30:56 -05:00
Rose Thompson
60f96112db
Moved the zero stage boot loader to the fpga directory.
2024-03-01 10:23:55 -06:00
Rose Thompson
cc7f433ce0
Update the fpga scripts to use the new derivative configs.
2024-01-31 13:19:28 -06:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
Rose Thompson
7693c5d4e2
Updates to fpga top level.
2023-12-15 15:32:05 -06:00
Rose Thompson
26cd22c388
Replaced fpga's verilog top with system verilog.
2023-12-15 13:42:52 -06:00
Rose Thompson
dab9d7ab3c
Replaced fpga top level verilog with system verilog.
2023-12-15 13:07:08 -06:00
Rose Thompson
34631c54d3
Get's the fpga building again after the git history rewrite.
2023-12-14 17:08:25 -06:00
Jacob Pease
7e494f2d3b
Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile.
2023-12-01 18:59:18 -06:00
Jacob Pease
71066cae12
Modified FPGA Makefile to override with relative path. FPGA boots now.
2023-11-30 17:51:15 -06:00
Rose Thompson
b137759b45
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-11-20 10:34:36 -06:00
Rose Thompson
cdd21d6635
Added menvcfg to debugger for checking what linux has configured.
2023-11-19 13:44:22 -06:00
Jacob Pease
87e6a5ccf2
Updated ROM to preload bootloader from file and infer a block ram when building for FPGA.
2023-11-18 19:15:39 -06:00
Jacob Pease
ff73f798ed
Replaced vivado-risc-v addins directory with new SDC repo.
2023-11-16 13:59:12 -06:00
Rose Thompson
d4bc9da085
Fixed another bug in the updated script changes.
2023-11-13 18:12:02 -06:00
Rose Thompson
f8b65f50b0
Fixed bugs in the updated fpga synthe script.
2023-11-13 18:10:22 -06:00
Rose Thompson
d5f0c15b90
Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
2023-11-13 17:48:28 -06:00
Rose Thompson
6b7ff50a84
Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.
2023-11-13 16:44:02 -06:00
Ross Thompson
d33c966a42
Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock.
2023-10-10 17:46:12 -05:00
Ross Thompson
055e00b8ac
Pushed vcu118 to 71MHz.
2023-08-25 17:04:50 -05:00
Jacob Pease
2bf6207919
Added help option to the flash-sd script.
2023-08-22 13:37:33 -05:00
Jacob Pease
e489ede51d
Merge branch 'main' of github.com:openhwgroup/cvw
2023-08-21 16:10:09 -05:00
David Harris
d801916d97
Merge pull request #383 from ross144/main
...
Adds Zicbom support for D-cache only. I-cache not yet supported. Tests 32 and 64 bit versions. Please rebuild regressions wally32 and wally64. To save rebuild time edit lines 11-12 of tests/riscof/Makefile
2023-08-21 13:32:00 -07:00
Ross Thompson
a16cde3dc6
Removed unused file.
2023-08-21 15:12:59 -05:00
Ross Thompson
1e0f1aeeac
Updated artyA7 debugger to match book.
2023-08-21 14:35:42 -05:00
Jacob Pease
144d93eba4
Added SPDX headers to other probe scripts.
2023-08-16 14:04:25 -05:00
Jacob Pease
f91157fc95
Added SPDX header to probe script.
2023-08-16 13:05:37 -05:00
Jacob Pease
c2f2bef433
Fixed bug caused by errant tab size in probe script.
2023-08-16 12:20:08 -05:00
