159 Commits

Author	SHA1	Message	Date
Ross Thompson	d6fa8d51d7	Modified sram1p1rw to support 3 different implementation styles. ... SRAM, Read first, and Write first.	2022-09-21 11:26:00 -05:00
Ross Thompson	2ae62c2869	pipelining of fetch into evict AHB requests.	2022-09-13 17:51:55 -05:00
Ross Thompson	8618045bf2	Optimization. Able to remove hptw address muxes from the E stage.	2022-09-08 15:51:18 -05:00
Ross Thompson	d6d1c5d66d	Moved files around.	2022-08-31 14:08:06 -05:00
Ross Thompson	68e54977fe	More cleanup.	2022-08-31 11:12:38 -05:00
Ross Thompson	0b41ed63f1	More simplifications.	2022-08-31 10:45:16 -05:00
Ross Thompson	ddd9c507fe	Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier.	2022-08-31 10:36:30 -05:00
Ross Thompson	6122c03e39	Removed unused old versions of the bus controllers.	2022-08-31 09:51:54 -05:00
Ross Thompson	1c248e5164	Removed old signals.	2022-08-31 09:50:39 -05:00
Ross Thompson	5b8f888e21	Maybe fixed it?	2022-08-30 18:08:34 -05:00
Ross Thompson	96793d15c0	more progress.	2022-08-30 17:32:32 -05:00
Ross Thompson	63a824cca1	More progress.	2022-08-30 15:27:19 -05:00
Ross Thompson	a532eb61ba	Progress.	2022-08-30 14:17:00 -05:00
Ross Thompson	c8a5d61cbb	new cache bus fsm not working but lints. ... Forgot a few files in the last commit.	2022-08-30 10:58:07 -05:00
David Harris	af2e71046e	Fixed rv32e LSU and IFU issues	2022-08-25 20:02:38 -07:00
David Harris	d7be94fab2	Cleaned up SelBusWord	2022-08-25 11:18:13 -07:00
David Harris	cd02c894df	renamed BusBuffer to FetchBuffer	2022-08-25 10:44:39 -07:00
Ross Thompson	bc0edc7bdf	Updated ila signals. ... Improve fpga wave config. added back in the fpga preload.	2022-08-25 09:03:29 -05:00
Ross Thompson	21526957cf	Updated fpga test bench. ... Solved read delay cache bug. Introduced during cache optimizations.	2022-08-21 15:59:54 -05:00
Ross Thompson	92c3cdc27d	Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.	2022-08-21 15:28:29 -05:00
Ross Thompson	96d6218078	Possible reduction of ignorerequest.	2022-08-19 18:07:44 -05:00
Ross Thompson	5301444a61	Changed signal names.	2022-08-17 16:12:04 -05:00
Ross Thompson	970a90dd72	Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.	2022-08-17 16:09:20 -05:00
Ross Thompson	acd920ae2f	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-01 22:09:11 -05:00
Ross Thompson	f7e64fcd69	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
Ross Thompson	171cf7413b	Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.	2022-08-01 21:08:14 -05:00
Katherine Parry	de03954946	re-added FStore2 in Cache	2022-07-29 22:54:49 +00:00
Ross Thompson	f1bd2524b7	Don't use this commit yet. Untested.	2022-07-24 15:40:52 -05:00
Ross Thompson	334008630f	Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.	2022-07-24 01:20:29 -05:00
Ross Thompson	856ac24686	Removed replay from the config files.	2022-07-24 00:34:11 -05:00
Ross Thompson	458bfbf6f6	Merged evict dirty clear with flush write back.	2022-07-24 00:22:43 -05:00
Ross Thompson	5cd6c8069d	signal name cleanup.	2022-07-22 23:36:27 -05:00
Ross Thompson	7d026e02f2	cache cleanup after removing replay on cpubusy.	2022-07-22 23:30:25 -05:00
Ross Thompson	706bc819e1	cache fsm cleanup after removal of replay.	2022-07-22 23:25:09 -05:00
Ross Thompson	0f586c9ed3	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
Ross Thompson	9868e685a4	Minor cleanup of cache.	2022-07-19 23:04:23 -05:00
Ross Thompson	6c8ac7851e	Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.	2022-07-19 22:42:25 -05:00
Ross Thompson	ffda64587c	Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.	2022-07-18 23:37:18 -05:00
Ross Thompson	a88543275f	Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.	2022-07-17 21:05:31 -05:00
Ross Thompson	3670c47141	Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.	2022-07-17 16:20:04 -05:00
Katherine Parry	2ada8a8bc1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-12 22:37:20 +00:00
David Harris	2bc8ff555b	added comment about checking SRAM size	2022-07-10 12:48:51 +00:00
David Harris	9cb675b2e4	added comment about RAMs in cacheway	2022-07-10 12:47:34 +00:00
Katherine Parry	ca4fe08fd9	renamed FLoad2 to FStore2	2022-07-09 00:26:45 +00:00
Katherine Parry	cd53ae67d9	moved fpu ieu write data mux to lsu	2022-07-08 23:56:57 +00:00
James Stine	c5dfefe669	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00
David Harris	3f9e662201	Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables	2022-07-08 08:44:37 +00:00
David Harris	96a75d7749	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-07 22:00:59 +00:00
Katherine Parry	08769e35ae	modified wally shared	2022-07-07 21:59:43 +00:00
David Harris	2f342c430e	fixing port errors	2022-07-07 21:57:10 +00:00