cvw/pipelined/src/cache
Ross Thompson c8a5d61cbb new cache bus fsm not working but lints.
Forgot a few files in the last commit.
2022-08-30 10:58:07 -05:00
..
AHBBuscachefsm.sv new cache bus fsm not working but lints. 2022-08-30 10:58:07 -05:00
AHBCachedp.sv new cache bus fsm not working but lints. 2022-08-30 10:58:07 -05:00
buscachefsm.sv Fixed rv32e LSU and IFU issues 2022-08-25 20:02:38 -07:00
cache.sv Cleaned up SelBusWord 2022-08-25 11:18:13 -07:00
cachedp.sv Fixed rv32e LSU and IFU issues 2022-08-25 20:02:38 -07:00
cachefsm.sv Updated fpga test bench. 2022-08-21 15:59:54 -05:00
cachereplacementpolicy.sv Fixed an issue with direct map cache's nextway logic. 2022-07-06 18:34:30 -05:00
cacheway.sv Fixed fstore2 in cache? 2022-08-01 22:04:44 -05:00
sram1p1rw.sv Updated ila signals. 2022-08-25 09:03:29 -05:00
subcachelineread.sv Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask. 2022-08-01 21:08:14 -05:00
ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00