Ross Thompson a88543275f Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.		2022-07-17 21:05:31 -05:00
..
cache.sv	renamed FLoad2 to FStore2	2022-07-09 00:26:45 +00:00
cachefsm.sv	Hacky fix to prevent ITLBMissF and TrapM bug.	2022-04-12 17:56:23 -05:00
cachereplacementpolicy.sv	Fixed an issue with direct map cache's nextway logic.	2022-07-06 18:34:30 -05:00
cacheway.sv	Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.	2022-07-17 21:05:31 -05:00
sram1p1rw.sv	added comment about checking SRAM size	2022-07-10 12:48:51 +00:00
subcachelineread.sv	Towards allowing dtim + bus.	2022-03-11 14:58:21 -06:00
ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00