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https://github.com/openhwgroup/cvw
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new cache bus fsm not working but lints.
Forgot a few files in the last commit.
This commit is contained in:
Ross Thompson
parent
5eb1fff27d
commit
c8a5d61cbb
161
pipelined/src/cache/AHBBuscachefsm.sv
vendored
Normal file
161
pipelined/src/cache/AHBBuscachefsm.sv
vendored
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@ -0,0 +1,161 @@
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///////////////////////////////////////////
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// busfsm.sv
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//
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// Written: Ross Thompson ross1728@gmail.com December 29, 2021
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// Modified:
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//
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// Purpose: Load/Store Unit's interface to BUS for cacheless system
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
|
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// substantial portions of the Software.
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||||
//
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||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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// HCLK and clk must be the same clock!
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module AHBBuscachefsm #(parameter integer WordCountThreshold,
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parameter integer LOGWPL, parameter logic CACHE_ENABLED )
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(input logic HCLK,
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input logic HRESETn,
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// IEU interface
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input logic [1:0] RW,
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input logic CPUBusy,
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output logic BusCommitted,
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output logic BusStall,
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output logic CaptureEn,
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// cache interface
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input logic [1:0] CacheRW,
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output logic CacheBusAck,
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// lsu interface
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input logic Cacheable,
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output logic SelUncachedAdr,
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output logic [LOGWPL-1:0] WordCount, WordCountDelayed,
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output logic SelBusWord,
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// BUS interface
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input logic HREADY,
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output logic [1:0] HTRANS,
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output logic HWRITE,
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output logic [2:0] HBURST
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);
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typedef enum logic [2:0] {STATE_READY,
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STATE_CAPTURE,
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STATE_DELAY,
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STATE_CPU_BUSY,
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STATE_CACHE_ACCESS} busstatetype;
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typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
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(* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
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logic WordCntEn;
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logic [LOGWPL-1:0] NextWordCount;
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logic WordCountFlag;
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logic [2:0] LocalBurstType;
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logic CntReset;
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assign CntReset = BusNextState == STATE_READY;
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// Used to send address for address stage of AHB.
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flopenr #(LOGWPL)
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WordCountReg(.clk(HCLK),
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.reset(~HRESETn | CntReset),
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.en(WordCntEn),
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.d(NextWordCount),
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.q(WordCount));
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// Used to store data from data phase of AHB.
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flopenr #(LOGWPL)
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WordCountDelayedReg(.clk(HCLK),
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.reset(~HRESETn | CntReset),
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.en(WordCntEn),
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.d(WordCount),
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.q(WordCountDelayed));
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assign NextWordCount = WordCount + 1'b1;
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assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0] ); // Detect when we are waiting on the final access.
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assign WordCntEn = (BusNextState == STATE_CACHE_ACCESS & HREADY) |
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(BusNextState == STATE_READY & |CacheRW & HREADY);
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always_ff @(posedge HCLK)
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if (~HRESETn) BusCurrState <= #1 STATE_READY;
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else BusCurrState <= #1 BusNextState;
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always_comb begin
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case(BusCurrState)
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STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE;
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else if (HREADY & |CacheRW) BusNextState = STATE_CACHE_ACCESS;
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else BusNextState = STATE_READY;
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STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY;
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else BusNextState = STATE_CAPTURE;
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STATE_DELAY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
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else BusNextState = STATE_READY;
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STATE_CPU_BUSY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
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else BusNextState = STATE_READY;
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STATE_CACHE_ACCESS: if(HREADY & WordCountFlag) BusNextState = STATE_READY;
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else BusNextState = STATE_CACHE_ACCESS;
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default: BusNextState = STATE_READY;
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endcase
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end
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assign BusStall = (BusCurrState == STATE_READY & (|RW | |CacheRW)) |
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(BusCurrState == STATE_CAPTURE) |
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(BusCurrState == STATE_CACHE_ACCESS);
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assign BusCommitted = BusCurrState != STATE_READY; // *** might not be correct
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assign HTRANS = (BusCurrState == STATE_READY & HREADY & |RW) |
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(BusCurrState == STATE_CAPTURE & ~HREADY) |
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(BusCurrState == STATE_CACHE_ACCESS & ~HREADY & |WordCount) ? AHB_NONSEQ :
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(BusCurrState == STATE_CACHE_ACCESS & ~HREADY & ~|WordCount) ? AHB_SEQ : AHB_IDLE;
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assign HWRITE = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) | // *** might not be necessary, maybe just RW[0]
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(BusCurrState == STATE_CACHE_ACCESS & CacheRW[0]);
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assign CaptureEn = BusCurrState == STATE_CAPTURE | (BusCurrState == STATE_CACHE_ACCESS & HREADY);
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assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0; // Don't want to use burst when doing an Uncached Access.
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always_comb begin
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case(WordCountThreshold)
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0: LocalBurstType = 3'b000;
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3: LocalBurstType = 3'b011; // INCR4
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7: LocalBurstType = 3'b101; // INCR8
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15: LocalBurstType = 3'b111; // INCR16
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default: LocalBurstType = 3'b001; // INCR without end.
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endcase
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end
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assign SelUncachedAdr = (BusCurrState == STATE_READY & |RW) |
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(BusCurrState == STATE_CAPTURE) |
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(BusCurrState == STATE_DELAY);
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assign CacheBusAck = (BusCurrState == STATE_CAPTURE & HREADY & WordCountFlag);
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assign SelBusWord = (BusCurrState == STATE_READY & RW[0]) |
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(BusCurrState == STATE_CAPTURE & RW[0]) |
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(BusCurrState == STATE_CACHE_ACCESS & CacheRW[0]);
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endmodule
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90
pipelined/src/cache/AHBCachedp.sv
vendored
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90
pipelined/src/cache/AHBCachedp.sv
vendored
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@ -0,0 +1,90 @@
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///////////////////////////////////////////
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// AHBCachedp.sv
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//
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// Written: Ross Thompson ross1728@gmail.com August 29, 2022
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// Modified:
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//
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// Purpose: Cache/Bus data path.
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// Bus Side logic
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// register the fetch data from the next level of memory.
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// This register should be necessary for timing. There is no register in the uncore or
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// ahblite controller between the memories and this cache.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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||||
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or
|
||||
// substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module AHBCachedp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
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(
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input logic HCLK, HRESETn,
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// bus interface
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input logic HREADY,
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input logic [`XLEN-1:0] HRDATA,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [1:0] HTRANS,
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output logic HWRITE,
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output logic [`PA_BITS-1:0] HADDR,
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output logic [LOGWPL-1:0] WordCount,
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// cache interface
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input logic [`PA_BITS-1:0] CacheBusAdr,
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input logic [1:0] CacheRW,
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output logic CacheBusAck,
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output logic [LINELEN-1:0] FetchBuffer,
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output logic SelUncachedAdr,
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// lsu/ifu interface
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input logic [`PA_BITS-1:0] PAdr,
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input logic [1:0] RW,
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input logic CPUBusy,
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input logic Cacheable,
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input logic [2:0] Funct3,
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output logic SelBusWord,
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output logic BusStall,
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output logic BusCommitted);
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localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0;
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logic [`PA_BITS-1:0] LocalHADDR;
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logic [LOGWPL-1:0] WordCountDelayed;
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logic CaptureEn;
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genvar index;
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for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
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logic [WORDSPERLINE-1:0] CaptureWord;
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assign CaptureWord[index] = CaptureEn & (index == WordCountDelayed);
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flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureWord[index]), .d(HRDATA),
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.q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN]));
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end
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mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdr, SelUncachedAdr, LocalHADDR);
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assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR;
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mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
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AHBBuscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
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.HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
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.CacheRW, .CacheBusAck, .Cacheable, .SelUncachedAdr, .WordCount, .WordCountDelayed,
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.HREADY, .HTRANS, .HWRITE, .HBURST);
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endmodule
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177
pipelined/src/ebu/ahbmultimanager.sv
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177
pipelined/src/ebu/ahbmultimanager.sv
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@ -0,0 +1,177 @@
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///////////////////////////////////////////
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// abhmultimanager
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//
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// Written: Ross Thompson August 29, 2022
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// ross1728@gmail.com
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// Modified:
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//
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// Purpose: AHB multi manager interface to merge LSU and IFU controls.
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// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
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// Arbitrates requests from instruction and data streams
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// Connects core to peripherals and I/O pins on SOC
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// Bus width presently matches XLEN
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// Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||
// software and associated documentation files (the "Software"), to deal in the Software
|
||||
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
||||
//
|
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// The above copyright notice and this permission notice shall be included in all copies or
|
||||
// substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
||||
// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ahbmultimanager
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(
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input logic clk, reset,
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// Signals from IFU
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input logic [`PA_BITS-1:0] IFUHADDR,
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input logic [2:0] IFUHBURST,
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input logic [1:0] IFUHTRANS,
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output logic IFUHREADY,
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// Signals from LSU
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input logic [`PA_BITS-1:0] LSUHADDR,
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input logic [`XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN
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input logic [`XLEN/8-1:0] LSUHWSTRB,
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input logic [2:0] LSUHSIZE,
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input logic [2:0] LSUHBURST,
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input logic [1:0] LSUHTRANS,
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input logic LSUHWRITE,
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output logic LSUHREADY,
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// add LSUHWSTRB ***
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// AHB-Lite external signals
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(* mark_debug = "true" *) input logic HREADY, HRESP,
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(* mark_debug = "true" *) output logic HCLK, HRESETn,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR, // *** one day switch to a different bus that supports the full physical address
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(* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
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(* mark_debug = "true" *) output logic [`XLEN/8-1:0] HWSTRB,
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(* mark_debug = "true" *) output logic HWRITE,
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(* mark_debug = "true" *) output logic [2:0] HSIZE,
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(* mark_debug = "true" *) output logic [2:0] HBURST,
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(* mark_debug = "true" *) output logic [3:0] HPROT,
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(* mark_debug = "true" *) output logic [1:0] HTRANS,
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(* mark_debug = "true" *) output logic HMASTLOCK
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);
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localparam ADRBITS = $clog2(`XLEN/8); // address bits for Byte Mask generator
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typedef enum logic [1:0] {IDLE, ARBITRATE} statetype;
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statetype BusState, NextBusState;
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logic LSUGrant;
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logic [ADRBITS-1:0] HADDRD;
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logic [1:0] HSIZED;
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logic [1:0] save, restore, dis, sel;
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logic both;
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logic DoArbitration;
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logic [`PA_BITS-1:0] IFUHADDRSave, IFUHADDRRestore;
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logic [1:0] IFUHTRANSSave, IFUHTRANSRestore;
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logic [2:0] IFUHBURSTSave, IFUHBURSTRestore;
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logic [`PA_BITS-1:0] LSUHADDRSave, LSUHADDRRestore;
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logic [1:0] LSUHTRANSSave, LSUHTRANSRestore;
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logic [2:0] LSUHBURSTSave, LSUHBURSTRestore;
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logic [2:0] LSUHSIZESave, LSUHSIZERestore;
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logic LSUHWRITESave, LSUHWRITERestore;
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logic IFUReq, LSUReq;
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logic IFUActive, LSUActive;
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assign HCLK = clk;
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assign HRESETn = ~reset;
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// if two requests come in at once pick one to select and save the others Address phase
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// inputs.
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// input stage IFU
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flopenr #(3+2+`PA_BITS) IFUSaveReg(HCLK, ~HRESETn, save[0],
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{IFUHBURST, IFUHTRANS, IFUHADDR},
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{IFUHBURSTSave, IFUHTRANSSave, IFUHADDRSave});
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mux2 #(3+2+`PA_BITS) IFURestorMux({IFUHBURST, IFUHTRANS, IFUHADDR},
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{IFUHBURSTSave, IFUHTRANSSave, IFUHADDRSave},
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restore[0],
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{IFUHBURSTRestore, IFUHTRANSRestore, IFUHADDRRestore});
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assign IFUReq = IFUHTRANSRestore != 2'b00;
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assign IFUHREADY = HREADY & ~dis[0];
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assign IFUActive = IFUReq & IFUHREADY;
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// input stage LSU
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flopenr #(1+3+3+2+`PA_BITS) LSUSaveReg(HCLK, ~HRESETn, save[1],
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{LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHADDR},
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{LSUHWRITESave, LSUHSIZESave, LSUHBURSTSave, LSUHTRANSSave, LSUHADDRSave});
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mux2 #(1+3+3+2+`PA_BITS) LSURestorMux({LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHADDR},
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{LSUHWRITESave, LSUHSIZESave, LSUHBURSTSave, LSUHTRANSSave, LSUHADDRSave},
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restore[1],
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{LSUHWRITERestore, LSUHSIZERestore, LSUHBURSTRestore, LSUHTRANSRestore, LSUHADDRRestore});
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assign LSUReq = LSUHTRANSRestore != 2'b00;
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assign LSUHREADY = HREADY & ~dis[1];
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assign LSUActive = LSUReq & LSUHREADY;
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assign both = LSUActive & IFUActive;
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// output mux //*** rewrite for general number of managers.
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assign HADDR = sel[1] ? LSUHADDRRestore : sel[0] ? IFUHADDRRestore : '0;
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assign HSIZE = sel[1] ? LSUHSIZERestore : sel[0] ? 3'b010: '0; // Instruction reads are always 32 bits
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assign HBURST = sel[1] ? LSUHBURSTRestore : sel[0] ? IFUHBURSTRestore : '0; // If doing memory accesses, use LSUburst, else use Instruction burst.
|
||||
assign HTRANS = sel[1] ? LSUHTRANSRestore : sel[0] ? IFUHTRANSRestore: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
|
||||
assign HPROT = 4'b0011; // not used; see Section 3.7
|
||||
assign HMASTLOCK = 0; // no locking supported
|
||||
assign HWRITE = sel[1] ? LSUHWRITERestore : sel[0] ? 1'b0 : '0;
|
||||
|
||||
// basic arb always selects LSU when both
|
||||
assign save[0] = BusState == IDLE & both;
|
||||
assign restore[0] = BusState == ARBITRATE;
|
||||
assign dis[0] = BusState == ARBITRATE;
|
||||
assign sel[0] = (NextBusState == ARBITRATE) ? 1'b0 : IFUReq;
|
||||
|
||||
//
|
||||
assign save[1] = 1'b0;
|
||||
assign restore[1] = 1'b0;
|
||||
assign dis[1] = 1'b0;
|
||||
assign sel[1] = NextBusState == ARBITRATE ? LSUReq : 1'b0;
|
||||
|
||||
|
||||
|
||||
// Bus State FSM
|
||||
// Data accesses have priority over instructions. However, if a data access comes
|
||||
// while an cache line read is occuring, the line read finishes before
|
||||
// the data access can take place.
|
||||
|
||||
flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);
|
||||
always_comb
|
||||
case (BusState)
|
||||
IDLE: if (both) NextBusState = ARBITRATE;
|
||||
else NextBusState = IDLE;
|
||||
ARBITRATE: if (HREADY)NextBusState = IDLE;
|
||||
else NextBusState = ARBITRATE;
|
||||
default: NextBusState = IDLE;
|
||||
endcase // case (BusState)
|
||||
|
||||
assign DoArbitration = BusState == ARBITRATE;
|
||||
|
||||
assign HWDATA = LSUHWDATA;
|
||||
assign HWSTRB = LSUHWSTRB;
|
||||
|
||||
|
||||
endmodule
|
||||
86
pipelined/src/lsu/AHBBusfsm.sv
Normal file
86
pipelined/src/lsu/AHBBusfsm.sv
Normal file
@ -0,0 +1,86 @@
|
||||
///////////////////////////////////////////
|
||||
// busfsm.sv
|
||||
//
|
||||
// Written: Ross Thompson ross1728@gmail.com December 29, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Load/Store Unit's interface to BUS for cacheless system
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// MIT LICENSE
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||
// software and associated documentation files (the "Software"), to deal in the Software
|
||||
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or
|
||||
// substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
||||
// OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
// HCLK and clk must be the same clock!
|
||||
module AHBBusfsm
|
||||
(input logic HCLK,
|
||||
input logic HRESETn,
|
||||
|
||||
// IEU interface
|
||||
input logic [1:0] RW,
|
||||
input logic CPUBusy,
|
||||
output logic BusCommitted,
|
||||
output logic BusStall,
|
||||
output logic CaptureEn,
|
||||
input logic HREADY,
|
||||
output logic [1:0] HTRANS,
|
||||
output logic HWRITE
|
||||
);
|
||||
|
||||
typedef enum logic [2:0] {STATE_READY,
|
||||
STATE_CAPTURE,
|
||||
STATE_DELAY,
|
||||
STATE_CPU_BUSY} busstatetype;
|
||||
|
||||
typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
|
||||
|
||||
(* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
|
||||
|
||||
always_ff @(posedge HCLK)
|
||||
if (~HRESETn) BusCurrState <= #1 STATE_READY;
|
||||
else BusCurrState <= #1 BusNextState;
|
||||
|
||||
always_comb begin
|
||||
case(BusCurrState)
|
||||
STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE;
|
||||
else BusNextState = STATE_READY;
|
||||
STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY;
|
||||
else BusNextState = STATE_CAPTURE;
|
||||
STATE_DELAY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
|
||||
else BusNextState = STATE_READY;
|
||||
STATE_CPU_BUSY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
|
||||
else BusNextState = STATE_READY;
|
||||
default: BusNextState = STATE_READY;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign BusStall = (BusCurrState == STATE_READY & |RW) |
|
||||
(BusCurrState == STATE_CAPTURE);
|
||||
|
||||
assign BusCommitted = BusCurrState != STATE_READY;
|
||||
|
||||
assign HTRANS = (BusCurrState == STATE_READY & HREADY & |RW) |
|
||||
(BusCurrState == STATE_CAPTURE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE;
|
||||
assign HWRITE = (BusCurrState == STATE_READY) & RW[0]; // *** might not be necessary, maybe just RW[0]
|
||||
assign CaptureEn = BusCurrState == STATE_CAPTURE;
|
||||
|
||||
endmodule
|
||||
@ -258,14 +258,14 @@ module lsu (
|
||||
.CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM),
|
||||
.FetchBuffer, .CacheFetchLine(DCacheFetchLine),
|
||||
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
|
||||
cachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) cachedp(
|
||||
.clk, .reset,
|
||||
.HRDATA, .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite),
|
||||
.BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete),
|
||||
AHBCachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) cachedp(
|
||||
.HCLK(clk), .HRESETn(~reset),
|
||||
.HRDATA,
|
||||
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
|
||||
.WordCount, .SelBusWord,
|
||||
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine),
|
||||
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM),
|
||||
.SelUncachedAdr, .IgnoreRequest, .RW(LSURWM), .CPUBusy, .Cacheable(CacheableM),
|
||||
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheRW({DCacheFetchLine, DCacheWriteLine} & ~{IgnoreRequest, IgnoreRequest}),
|
||||
.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM),
|
||||
.SelUncachedAdr, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}), .CPUBusy, .Cacheable(CacheableM),
|
||||
.BusStall, .BusCommitted(BusCommittedM));
|
||||
|
||||
mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user