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cache fsm cleanup after removal of replay.

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This commit is contained in:
Ross Thompson 2022-07-22 23:25:09 -05:00
parent 0f586c9ed3
commit 706bc819e1
1 changed files with 2 additions and 26 deletions
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28
pipelined/src/cache/cachefsm.sv vendored
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@ -92,13 +92,7 @@ module cachefsm
STATE_MISS_FETCH_WDV,
STATE_MISS_EVICT_DIRTY_START,
STATE_MISS_EVICT_DIRTY,
STATE_MISS_EVICT_DIRTY_DONE,
STATE_MISS_WRITE_CACHE_LINE,
STATE_MISS_READ_WORD,
STATE_MISS_READ_WORD_DELAY,
STATE_MISS_WRITE_WORD,
// cpu stalled replay/restore state
STATE_CPU_BUSY,
// flush cache
STATE_FLUSH,
STATE_FLUSH_CHECK,
@ -142,24 +136,15 @@ module cachefsm
case (CurrState)
STATE_READY: if(IgnoreRequest | InvalidateCache) NextState = STATE_READY;
else if(DoFlush) NextState = STATE_FLUSH;
//else if(DoAnyHit & CPUBusy) NextState = STATE_CPU_BUSY;
else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // fetch first, then eviction is necessary. see delay in lru read/write path.
else NextState = STATE_READY;
STATE_MISS_FETCH_WDV: if(CacheBusAck & ~VictimDirty) NextState = STATE_MISS_WRITE_CACHE_LINE;
else if(CacheBusAck & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY_START;
else NextState = STATE_MISS_FETCH_WDV;
STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY; // cpu_busy not needed. load misses have the property of reading from the bus buffer rather than sram.
STATE_MISS_READ_WORD: if(CacheRW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD;
else NextState = STATE_MISS_READ_WORD_DELAY;
STATE_MISS_READ_WORD_DELAY: if(CPUBusy) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE;
else NextState = STATE_MISS_EVICT_DIRTY;
STATE_MISS_EVICT_DIRTY_START: NextState = STATE_MISS_EVICT_DIRTY; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
STATE_FLUSH: NextState = STATE_FLUSH_CHECK;
STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK;
else if(FlushFlag) NextState = STATE_READY;
@ -182,7 +167,6 @@ module cachefsm
(CurrState == STATE_MISS_EVICT_DIRTY_START) |
(CurrState == STATE_MISS_EVICT_DIRTY) |
(CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
(CurrState == STATE_MISS_READ_WORD) |
(CurrState == STATE_FLUSH) |
(CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) |
(CurrState == STATE_FLUSH_INCR) |
@ -191,7 +175,6 @@ module cachefsm
// write enables internal to cache
assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE;
assign SetDirty = (CurrState == STATE_READY & DoAnyUpdateHit) |
(CurrState == STATE_MISS_READ_WORD_DELAY & AMO) |
(CurrState == STATE_MISS_WRITE_CACHE_LINE & (AMO | CacheRW[0]));
assign ClearValid = '0;
assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) |
@ -216,10 +199,8 @@ module cachefsm
assign CacheWriteLine = (CurrState == STATE_MISS_EVICT_DIRTY_START) |
(CurrState == STATE_FLUSH_CHECK & VictimDirty);
// handle cpu stall.
assign restore = ((CurrState == STATE_CPU_BUSY)) & ~`REPLAY;
assign save = ((CurrState == STATE_READY & DoAnyHit & CPUBusy) |
(CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | CacheRW[1]) & CPUBusy) |
(CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
assign restore = '0;
assign save = '0;
// **** can this be simplified?
assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss.
@ -231,11 +212,6 @@ module cachefsm
(CurrState == STATE_MISS_EVICT_DIRTY) |
(CurrState == STATE_MISS_EVICT_DIRTY_START) |
(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
(CurrState == STATE_MISS_READ_WORD) |
(CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) |
(CurrState == STATE_MISS_WRITE_WORD) |
(CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) |
resetDelay;
assign SelBusBuffer = CurrState == STATE_MISS_WRITE_CACHE_LINE;