David Harris
17c9be7695
Cleanup typos, remove Zicond from riscof until it is working
2024-01-18 21:36:52 -08:00
David Harris
0588d611ea
Zfa fli support working for F and D
2024-01-16 17:27:40 -08:00
David Harris
da4eca4854
Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
2024-01-15 13:24:57 -08:00
David Harris
9eb6d9c8b8
Added Zicond support
2024-01-11 07:37:15 -08:00
David Harris
d93684be21
Verilate running (slowly)
2024-01-07 21:30:33 -08:00
David Harris
7cd02351d9
Updated testbench to count size of signature without searching for x. Now runs with Verilator.
2024-01-07 09:00:19 -08:00
David Harris
caedab679a
Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x
2024-01-07 07:14:12 -08:00
David Harris
34f97201ee
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-01-06 08:19:56 -08:00
David Harris
167e061a1c
Fixed truncated begin_signature in testbench
2024-01-06 08:19:46 -08:00
Rose Thompson
ab07d64195
Fixes coremark. Maybe works with verilator.
2024-01-06 00:41:57 -06:00
David Harris
ed623f1a71
Fixed unsupported riscof YAML string; preparing for Verilator -G testcase
2024-01-05 20:06:21 -08:00
David Harris
8552369687
Merged PR538, delete unused tests
2023-12-20 13:30:31 -08:00
Rose Thompson
70d0169019
All regression tests which matter are running!
2023-12-20 14:57:52 -06:00
Rose Thompson
1b59182d59
Updated tests with ending label.
2023-12-20 14:55:37 -06:00
Rose Thompson
b68dd74f89
Reverted logic to bit change.
2023-12-20 13:16:32 -06:00
Rose Thompson
a8ab3c8342
Ok that is a stange bug.
...
The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue.
2023-12-20 12:25:34 -06:00
Rose Thompson
9ee1ffe8fe
Almost working with modelsim and verilator.
2023-12-20 11:29:31 -06:00
David Harris
5dbca251d8
Defined new Zicboz and Zcb tests
2023-12-19 13:24:11 -08:00
Rose Thompson
2e792606dd
More progress. Most tests are passing in modelsim.
2023-12-19 12:06:00 -06:00
Rose Thompson
74238defc3
Progress.
2023-12-18 20:23:19 -06:00
Rose Thompson
1e1759c258
Restored the one hack change which prevents verilator from working.
2023-12-18 17:00:53 -06:00
Rose Thompson
408bb2c35b
Yay! I got verilator to compile our testbench! Does it actually work I don't know.
2023-12-18 16:44:34 -06:00
Rose Thompson
c1ac153a4f
Closer to verilator support.
2023-12-18 16:26:56 -06:00
Rose Thompson
5062a8c89c
Added parameter for cache's SRAM length.
...
Progress towards verilator support.
2023-12-18 12:50:49 -06:00
David Harris
38f4d9baf8
Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e
2023-12-15 05:05:53 -08:00
David Harris
68d96a929c
Fixed hierarchical path to EcallFaultM in testbench
2023-12-13 16:37:54 -08:00
David Harris
ff26baf7e8
Rolled back attempt to support Verilator
2023-12-13 12:53:44 -08:00
David Harris
aff61ea97a
Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator
2023-12-13 11:33:59 -08:00
Jacob Pease
a1e7158bd9
Merge branch 'main' of github.com:openhwgroup/cvw
2023-11-18 19:20:48 -06:00
Rose Thompson
38b327eaf8
Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters.
2023-11-17 11:21:25 -06:00
Jacob Pease
23e5fca2a7
Merge branch 'main' of github.com:jacobpease/cvw
2023-11-16 14:04:11 -06:00
Rose Thompson
da59cb71a9
Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.
2023-11-13 14:12:27 -06:00
David Harris
4de21c206f
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-11-03 16:04:10 -07:00
David Harris
dd072c80f2
Updated testbenches to capture InstrM because it may be optimized out of IFU
2023-11-03 05:24:15 -07:00
naichewa
a08356fdaa
correct exclusion tags and reset testbench
2023-11-01 10:34:39 -07:00
naichewa
e3d8162279
harris code review 3
2023-11-01 10:14:15 -07:00
naichewa
2330f4ee63
hardware interlock
2023-10-30 17:00:20 -07:00
Jacob Pease
3e891ee635
Merge branch 'main' of github.com:openhwgroup/cvw
2023-10-17 14:13:28 -05:00
Jacob Pease
2b1c604016
Slight modification to testbench.sv
2023-10-17 14:13:18 -05:00
naichewa
0ff9ce527d
Merge branch 'main' into spi
2023-10-16 22:59:50 -07:00
naichewa
4941fe1769
sync fifo passes
2023-10-16 22:57:02 -07:00
David Harris
fab9fbd7f1
Merged testbench
2023-10-16 13:52:24 -07:00
David Harris
ac4216b43d
Incorporated new AMO tests from riscv-arch-test
2023-10-16 10:25:45 -07:00
Rose Thompson
c1d6fddea8
Removed P.FPGA from testbench.
2023-10-13 14:08:17 -05:00
naichewa
d5d4f9d044
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
b756b248b4
Wow. The newest version of Vivado does not like the enums as parameters.
...
The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
Ross Thompson
9a49ec0b98
Removed duplicate signal name from testbench.
2023-07-07 16:34:08 -05:00
Ross Thompson
2ce8b66574
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-07-06 14:55:43 -05:00
David Harris
001d3cfdc5
Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder
2023-07-02 13:29:27 -07:00
