Ross Thompson
822d989383
Added comment.
2022-09-20 09:49:53 -05:00
Ross Thompson
57c366c1b2
Removed NonIROM and NonDTIM select signals from IFU and LSU.
2022-09-17 22:01:03 -05:00
Ross Thompson
cb34b7c98f
Found the ahb burst bug.
...
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
2022-09-17 20:30:01 -05:00
David Harris
8f2b3b2387
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-15 12:49:21 -07:00
David Harris
94dca9194e
renamed endianswap
2022-09-15 12:49:18 -07:00
Ross Thompson
38e114a6c0
Fixed subword read to work with bigendian.
2022-09-15 14:08:04 -05:00
Ross Thompson
c7d3580637
Renamed signals in the LSU.
2022-09-13 11:47:39 -05:00
Ross Thompson
7f1ae039b0
Optimization. Able to remove hptw address muxes from the E stage.
2022-09-08 15:51:18 -05:00
Ross Thompson
f4e3036593
Oups fixed order of ending swap with mux between cache and fetch buffer.
2022-09-07 16:29:47 -05:00
Ross Thompson
d601fdf186
Possible fix to AHB burst eviction bug. If HREADY went low during a burst seq the next data phase would only last 1 cycle.
2022-09-02 19:58:41 -05:00
Ross Thompson
055b55402f
clean up subword write.
2022-09-01 17:55:19 -05:00
Ross Thompson
eae56a890c
marked possible improvement to ahb bus fsms.
2022-08-31 23:57:08 -05:00
Ross Thompson
12d1ef2144
More renaming.
2022-08-31 14:49:08 -05:00
Ross Thompson
c03b202ab0
Moved files.
...
Encapsulated ahbinterface.
2022-08-31 14:45:01 -05:00
Ross Thompson
f2f1169a04
Renamed AHBCachebusdp to abhcacheinterface.
2022-08-31 14:12:19 -05:00
Ross Thompson
a0f681944c
More Cleanup.
2022-08-31 11:21:02 -05:00
Ross Thompson
8156109add
More cleanup.
2022-08-31 11:12:38 -05:00
Ross Thompson
89f13370e2
Removed old signals.
2022-08-31 09:50:39 -05:00
Ross Thompson
5409501ca6
Maybe fixed it?
2022-08-30 18:08:34 -05:00
Ross Thompson
8b9f30c91a
more progress.
2022-08-30 17:32:32 -05:00
Ross Thompson
315f662eb9
More progress.
2022-08-30 15:27:19 -05:00
Ross Thompson
637d60b64c
Progress.
2022-08-30 14:17:00 -05:00
Ross Thompson
8cf3c7b352
new cache bus fsm not working but lints.
...
Forgot a few files in the last commit.
2022-08-30 10:58:07 -05:00
Ross Thompson
a2220fc142
Have a rough working multi manager!
2022-08-29 17:11:27 -05:00
Ross Thompson
f5584bb41c
Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu.
2022-08-29 17:04:53 -05:00
Ross Thompson
233777f744
Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager.
2022-08-29 13:01:24 -05:00
Ross Thompson
e805f33f4e
Typo.
2022-08-29 11:40:35 -05:00
Ross Thompson
e7de0e033e
Added comments about planned changes.
2022-08-29 09:48:00 -05:00
Ross Thompson
7b76fbaa9a
Removed ignore request from busfsm.
2022-08-28 21:12:27 -05:00
Ross Thompson
122c88ee46
Created two new pma regions for dtim and irom.
2022-08-28 13:50:50 -05:00
Ross Thompson
dd7736cb93
Possible fix.
2022-08-28 13:10:47 -05:00
Ross Thompson
a81fcc6b4b
Partial fix to bus + dtim.
2022-08-27 23:44:17 -05:00
David Harris
f2517f8290
Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
2022-08-27 20:31:09 -07:00
David Harris
60b673cafd
Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus
2022-08-27 05:31:56 -07:00
David Harris
812158aeee
Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
2022-08-26 20:26:12 -07:00
David Harris
95dd50a567
Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
2022-08-26 20:12:03 -07:00
David Harris
ca6837f597
Fixed endian swapping on bus only
2022-08-26 19:58:04 -07:00
David Harris
5f37e16b62
Fixed rv32e LSU and IFU issues
2022-08-25 20:02:38 -07:00
David Harris
671ea60f3e
lsu simplification
2022-08-25 18:52:42 -07:00
David Harris
f262abb5c3
Removed unused signals
2022-08-25 18:34:39 -07:00
David Harris
b73286ece6
Removed unused signals
2022-08-25 18:30:46 -07:00
David Harris
cfcde754c3
Removed CacheBusAck
2022-08-25 18:17:34 -07:00
David Harris
9bc62ce124
Removed SelUncachedAdr
2022-08-25 18:15:59 -07:00
David Harris
f39e62eeea
Removed Cache_Enabled
2022-08-25 18:13:34 -07:00
David Harris
85e93e2bb7
Removed CacheFetchLine and CacheWriteLine
2022-08-25 18:10:15 -07:00
David Harris
e485e986a5
Removed wordcount
2022-08-25 18:04:49 -07:00
David Harris
5340c45dfc
Separated busdp for cache from simpler logic for no cache
2022-08-25 17:54:04 -07:00
David Harris
9a92bfe095
Simplified swbytemask
2022-08-25 17:32:16 -07:00
Ross Thompson
5c2bc20dbd
Almost fixed issues with irom and dtim address selection.
2022-08-25 15:52:25 -05:00
Ross Thompson
f67010c688
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 14:40:52 -05:00
David Harris
bc0c7d0cd8
Cleaned up SelBusWord
2022-08-25 11:18:13 -07:00
David Harris
c442dea173
Removed M sufix from busdp signals
2022-08-25 11:13:01 -07:00
David Harris
48f346baf8
Renamed LSUFunct3M to Funct3 in busdp
2022-08-25 11:08:12 -07:00
David Harris
9bada9c14a
Renaming LSU signals from busdp
2022-08-25 11:05:10 -07:00
David Harris
3ba961d1a8
renamed BusBuffer to FetchBuffer
2022-08-25 10:44:39 -07:00
David Harris
dda3b441d7
Continued busdp/ebu simplification
2022-08-25 10:20:02 -07:00
David Harris
aba914ea5e
Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
2022-08-25 09:52:08 -07:00
Ross Thompson
e605ef57dc
BROKEN. Don't use this commit.
...
Issue running cacheless with bus.
2022-08-25 11:02:46 -05:00
David Harris
ae0702d129
Renamed DCache to Cache in busdp/busfsm signal interface
2022-08-25 06:21:22 -07:00
David Harris
1206b388c7
Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM
2022-08-25 04:06:27 -07:00
David Harris
f7209627c2
removed simpleram and modified dtim to use bram1p1rw
2022-08-25 03:39:57 -07:00
Ross Thompson
769af32f2a
Renamed RAM to UNCORE_RAM.
2022-08-24 18:09:07 -05:00
Ross Thompson
51adf6cba9
Modified the lsu/ifu memory configurations.
2022-08-24 12:35:15 -05:00
David Harris
c61dba6192
Fixed LSU typos
2022-08-23 10:23:08 -07:00
Ross Thompson
aa5cbab0d8
Replaced LSU data replication with 0 extention.
2022-08-23 10:43:47 -05:00
Ross Thompson
3b07584403
Updated the names of the *WriteDataM inside the LSU to more meaningful names.
...
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
2022-08-23 10:34:39 -05:00
David Harris
e714b75888
LSU minor edits
2022-08-23 07:35:47 -07:00
David Harris
0e489443f2
Finished FPU-LSU interface cleanup
2022-08-22 13:43:04 -07:00
David Harris
8444eca57c
Simplified FPU-LSU interface to skip IEU
2022-08-22 13:29:20 -07:00
Ross Thompson
ebe4339953
Updated fpga test bench.
...
Solved read delay cache bug. Introduced during cache optimizations.
2022-08-21 15:59:54 -05:00
Ross Thompson
2ba390adf4
Possible reduction of ignorerequest.
2022-08-19 18:07:44 -05:00
Ross Thompson
517c0f6c35
Changed signal names.
2022-08-17 16:12:04 -05:00
Ross Thompson
f6e5746e59
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
2022-08-17 16:09:20 -05:00
Ross Thompson
57fcf0ef79
Fixed fstore2 in cache?
2022-08-01 22:04:44 -05:00
Ross Thompson
797d9e3610
Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.
2022-08-01 21:12:25 -05:00
Ross Thompson
3cd8404917
Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
2022-08-01 21:08:14 -05:00
Ross Thompson
3612db2d70
pulled swbbytemask out of subword write.
2022-08-01 20:48:45 -05:00
Ross Thompson
05484c4c05
signal name cleanup.
2022-07-22 23:36:27 -05:00
Katherine Parry
12a54161c0
found the bug in the store modification
2022-07-12 22:42:19 +00:00
Katherine Parry
62205ebb3b
renamed FLoad2 to FStore2
2022-07-09 00:26:45 +00:00
Katherine Parry
97e7e619d9
moved fpu ieu write data mux to lsu
2022-07-08 23:56:57 +00:00
David Harris
72e216d053
APB CLINT passing regression
2022-07-05 15:51:35 +00:00
Katherine Parry
8f98f3bfab
added rv32 double precision stores - untested
2022-06-28 21:33:31 +00:00
Katherine Parry
03d823f5d7
added fld in rv32 - needs testing
2022-06-20 22:53:13 +00:00
slmnemo
be658d3933
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
slmnemo
a5aa75e5de
Merge branch 'main' into cacheburstmode
2022-06-08 02:21:33 +00:00
slmnemo
1d22fc707a
Added lock signal to ensure AHB speaks with the right bus
2022-06-08 02:19:21 +00:00
slmnemo
90c5e5d319
Reworked bus to handle burst interfacing
2022-06-07 11:22:53 +00:00
David Harris
129fab3794
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
2022-06-02 14:18:55 +00:00
slmnemo
efce3e4953
added LSUBurstDone signal to signal when a burst has finished
2022-05-26 16:29:13 -07:00
slmnemo
80965f953c
added burst size signals to the IFU, EBU, LSU, and busdp
2022-05-25 18:02:50 -07:00
David Harris
5acb526375
More unused signal cleanup
2022-05-12 15:21:09 +00:00
David Harris
fb725a9e0a
Clean up unused signals
2022-05-12 14:49:58 +00:00
David Harris
8066ba45e8
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
David Harris
462158ea92
LSU name cleanup
2022-04-18 03:18:38 +00:00
David Harris
2882460c94
Renamed FinalAMOWriteDataM to AMOWriteDataM
2022-04-18 01:30:03 +00:00
Ross Thompson
b9a19304db
Fixed possible bugs in LRSC.
2022-04-16 14:45:31 -05:00
Ross Thompson
ab9738d3be
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
7a824eaae1
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
2022-03-24 23:47:28 -05:00
Ross Thompson
58668812c1
Moved WriteDataM register into LSU.
2022-03-23 14:17:59 -05:00
