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316 Commits

Author SHA1 Message Date
Ross Thompson
b48d6b5e1f Solved the sram write first / read first issue. Works correctly with read first now. 2022-09-22 14:16:26 -05:00
Ross Thompson
99e01dd31f Cleaned up the IFU and LSU around dtim and irom address calculation. 2022-09-21 18:23:56 -05:00
Ross Thompson
ac864a6ca3 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00
Ross Thompson
980b35d585 Merge branch 'tempMain' into main 2022-09-20 13:57:38 -05:00
Ross Thompson
426ec6222b Added chip enables to sram. 2022-09-20 10:49:14 -05:00
Ross Thompson
822d989383 Added comment. 2022-09-20 09:49:53 -05:00
Ross Thompson
57c366c1b2 Removed NonIROM and NonDTIM select signals from IFU and LSU. 2022-09-17 22:01:03 -05:00
Ross Thompson
cb34b7c98f Found the ahb burst bug. 
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests.  It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads.  The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads.  In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
 2022-09-17 20:30:01 -05:00
David Harris
8f2b3b2387 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-15 12:49:21 -07:00
David Harris
94dca9194e renamed endianswap 2022-09-15 12:49:18 -07:00
Ross Thompson
38e114a6c0 Fixed subword read to work with bigendian. 2022-09-15 14:08:04 -05:00
Ross Thompson
c7d3580637 Renamed signals in the LSU. 2022-09-13 11:47:39 -05:00
Ross Thompson
7f1ae039b0 Optimization. Able to remove hptw address muxes from the E stage. 2022-09-08 15:51:18 -05:00
Ross Thompson
f4e3036593 Oups fixed order of ending swap with mux between cache and fetch buffer. 2022-09-07 16:29:47 -05:00
Ross Thompson
d601fdf186 Possible fix to AHB burst eviction bug. If HREADY went low during a burst seq the next data phase would only last 1 cycle. 2022-09-02 19:58:41 -05:00
Ross Thompson
055b55402f clean up subword write. 2022-09-01 17:55:19 -05:00
Ross Thompson
eae56a890c marked possible improvement to ahb bus fsms. 2022-08-31 23:57:08 -05:00
Ross Thompson
12d1ef2144 More renaming. 2022-08-31 14:49:08 -05:00
Ross Thompson
c03b202ab0 Moved files. 
Encapsulated ahbinterface.
 2022-08-31 14:45:01 -05:00
Ross Thompson
f2f1169a04 Renamed AHBCachebusdp to abhcacheinterface. 2022-08-31 14:12:19 -05:00
Ross Thompson
1b339f0547 Moved files around. 2022-08-31 14:08:06 -05:00
Ross Thompson
a0f681944c More Cleanup. 2022-08-31 11:21:02 -05:00
Ross Thompson
8156109add More cleanup. 2022-08-31 11:12:38 -05:00
Ross Thompson
ed2a9225ea Removed unused old versions of the bus controllers. 2022-08-31 09:51:54 -05:00
Ross Thompson
89f13370e2 Removed old signals. 2022-08-31 09:50:39 -05:00
Ross Thompson
5409501ca6 Maybe fixed it? 2022-08-30 18:08:34 -05:00
Ross Thompson
8b9f30c91a more progress. 2022-08-30 17:32:32 -05:00
Ross Thompson
315f662eb9 More progress. 2022-08-30 15:27:19 -05:00
Ross Thompson
637d60b64c Progress. 2022-08-30 14:17:00 -05:00
Ross Thompson
8cf3c7b352 new cache bus fsm not working but lints. 
Forgot a few files in the last commit.
 2022-08-30 10:58:07 -05:00
Ross Thompson
a2220fc142 Have a rough working multi manager! 2022-08-29 17:11:27 -05:00
Ross Thompson
f5584bb41c Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu. 2022-08-29 17:04:53 -05:00
Ross Thompson
233777f744 Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager. 2022-08-29 13:01:24 -05:00
Ross Thompson
e805f33f4e Typo. 2022-08-29 11:40:35 -05:00
Ross Thompson
e7de0e033e Added comments about planned changes. 2022-08-29 09:48:00 -05:00
Ross Thompson
7b76fbaa9a Removed ignore request from busfsm. 2022-08-28 21:12:27 -05:00
Ross Thompson
122c88ee46 Created two new pma regions for dtim and irom. 2022-08-28 13:50:50 -05:00
Ross Thompson
dd7736cb93 Possible fix. 2022-08-28 13:10:47 -05:00
Ross Thompson
a81fcc6b4b Partial fix to bus + dtim. 2022-08-27 23:44:17 -05:00
David Harris
f2517f8290 Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00
David Harris
60b673cafd Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus 2022-08-27 05:31:56 -07:00
David Harris
03e731b3ff Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM 2022-08-26 21:05:20 -07:00
David Harris
812158aeee Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
David Harris
95dd50a567 Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem 2022-08-26 20:12:03 -07:00
David Harris
ca6837f597 Fixed endian swapping on bus only 2022-08-26 19:58:04 -07:00
David Harris
5f37e16b62 Fixed rv32e LSU and IFU issues 2022-08-25 20:02:38 -07:00
David Harris
671ea60f3e lsu simplification 2022-08-25 18:52:42 -07:00
David Harris
ec2c6d4fcb busfsm simplified 2022-08-25 18:36:53 -07:00
David Harris
f262abb5c3 Removed unused signals 2022-08-25 18:34:39 -07:00
David Harris
b73286ece6 Removed unused signals 2022-08-25 18:30:46 -07:00
David Harris
949e76bc83 Removed UncachedBusRead and UncachedBusWrite 2022-08-25 18:24:39 -07:00
David Harris
e39694694c Restored ahbtranstype 2022-08-25 18:22:26 -07:00
David Harris
83d3782f2c Removed ahbtranstype 2022-08-25 18:21:45 -07:00
David Harris
543fbd1fa9 Removed WordCountFlag 2022-08-25 18:21:18 -07:00
David Harris
d118fcbde8 Removed UncachedAccess 2022-08-25 18:20:52 -07:00
David Harris
bac95823b6 Removed UncachedRW 2022-08-25 18:19:41 -07:00
David Harris
cfcde754c3 Removed CacheBusAck 2022-08-25 18:17:34 -07:00
David Harris
9bc62ce124 Removed SelUncachedAdr 2022-08-25 18:15:59 -07:00
David Harris
f39e62eeea Removed Cache_Enabled 2022-08-25 18:13:34 -07:00
David Harris
5bfaf31df0 Removed STATE_BUS_FETCH and STATE_BUS_WRITE 2022-08-25 18:12:09 -07:00
David Harris
85e93e2bb7 Removed CacheFetchLine and CacheWriteLine 2022-08-25 18:10:15 -07:00
David Harris
23a102b1b9 Removed CountEn 2022-08-25 18:05:44 -07:00
David Harris
e485e986a5 Removed wordcount 2022-08-25 18:04:49 -07:00
David Harris
69dff87feb Added buscachefsm for system with bus and cache 2022-08-25 18:01:01 -07:00
David Harris
5340c45dfc Separated busdp for cache from simpler logic for no cache 2022-08-25 17:54:04 -07:00
David Harris
9a92bfe095 Simplified swbytemask 2022-08-25 17:32:16 -07:00
David Harris
eb753b3b3f FIxed wallypipelinedsoc merge conflict 2022-08-25 15:36:47 -07:00
David Harris
902d2067ba Removed delayed AHB signals from top level 2022-08-25 15:34:14 -07:00
Ross Thompson
5c2bc20dbd Almost fixed issues with irom and dtim address selection. 2022-08-25 15:52:25 -05:00
Ross Thompson
d23888407b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 14:45:02 -05:00
David Harris
1226b2889e ahblite cleanup 2022-08-25 12:44:25 -07:00
Ross Thompson
f67010c688 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 14:40:52 -05:00
David Harris
bc0c7d0cd8 Cleaned up SelBusWord 2022-08-25 11:18:13 -07:00
David Harris
c442dea173 Removed M sufix from busdp signals 2022-08-25 11:13:01 -07:00
David Harris
48f346baf8 Renamed LSUFunct3M to Funct3 in busdp 2022-08-25 11:08:12 -07:00
David Harris
9bada9c14a Renaming LSU signals from busdp 2022-08-25 11:05:10 -07:00
David Harris
3ba961d1a8 renamed BusBuffer to FetchBuffer 2022-08-25 10:44:39 -07:00
David Harris
dda3b441d7 Continued busdp/ebu simplification 2022-08-25 10:20:02 -07:00
David Harris
aba914ea5e Renamed AHB signals coming out of LSU to LSH_<AHBNAME> 2022-08-25 09:52:08 -07:00
Ross Thompson
e605ef57dc BROKEN. Don't use this commit. 
Issue running cacheless with bus.
 2022-08-25 11:02:46 -05:00
David Harris
ae0702d129 Renamed DCache to Cache in busdp/busfsm signal interface 2022-08-25 06:21:22 -07:00
David Harris
db5c941d6f Minor name cleanups 2022-08-25 04:28:25 -07:00
David Harris
1206b388c7 Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM 2022-08-25 04:06:27 -07:00
David Harris
f7209627c2 removed simpleram and modified dtim to use bram1p1rw 2022-08-25 03:39:57 -07:00
Ross Thompson
769af32f2a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
51adf6cba9 Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
Ross Thompson
e4cbb43c67 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 18:52:15 -05:00
Ross Thompson
642dc170d7 Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite. 2022-08-23 18:51:11 -05:00
David Harris
c61dba6192 Fixed LSU typos 2022-08-23 10:23:08 -07:00
Ross Thompson
aa5cbab0d8 Replaced LSU data replication with 0 extention. 2022-08-23 10:43:47 -05:00
Ross Thompson
3b07584403 Updated the names of the *WriteDataM inside the LSU to more meaningful names. 
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
 2022-08-23 10:34:39 -05:00
David Harris
e714b75888 LSU minor edits 2022-08-23 07:35:47 -07:00
David Harris
3c91df95d9 Named HTRANS states in busfsm 2022-08-22 13:56:46 -07:00
David Harris
0e489443f2 Finished FPU-LSU interface cleanup 2022-08-22 13:43:04 -07:00
David Harris
8444eca57c Simplified FPU-LSU interface to skip IEU 2022-08-22 13:29:20 -07:00
Ross Thompson
ebe4339953 Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
2ba390adf4 Possible reduction of ignorerequest. 2022-08-19 18:07:44 -05:00
Ross Thompson
517c0f6c35 Changed signal names. 2022-08-17 16:12:04 -05:00
Ross Thompson
f6e5746e59 Better name for LSUBusWriteCrit. Changed to SelLSUBusWord. 2022-08-17 16:09:20 -05:00
Ross Thompson
299aefb76a Removed old code from interlockfsm. 2022-08-17 12:52:56 -05:00