Ross Thompson 517c0f6c35 Changed signal names.		2022-08-17 16:12:04 -05:00
..
atomic.sv	Clean up unused signals	2022-05-12 14:49:58 +00:00
bigendianswap.sv	added fld in rv32 - needs testing	2022-06-20 22:53:13 +00:00
busdp.sv	Changed signal names.	2022-08-17 16:12:04 -05:00
busfsm.sv	Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.	2022-08-17 16:09:20 -05:00
dtim.sv	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
interlockfsm.sv	Removed old code from interlockfsm.	2022-08-17 12:52:56 -05:00
lrsc.sv	Clean up unused signals	2022-05-12 14:49:58 +00:00
lsu.sv	Changed signal names.	2022-08-17 16:12:04 -05:00
lsuvirtmen.sv	Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.	2022-03-24 23:47:28 -05:00
subwordread.sv	added rv32 double precision stores - untested	2022-06-28 21:33:31 +00:00
subwordwrite.sv	pulled swbbytemask out of subword write.	2022-08-01 20:48:45 -05:00
swbytemask.sv	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
swbytemaskword.sv	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00