bbracker
71ef87bc55
testbench workaround for QEMU's SSTATUS XLEN bits
2021-07-23 14:00:44 -04:00
kipmacsaigoren
3bb6c8b32f
Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's
2021-07-23 11:57:58 -05:00
David Harris
5306d42bfe
Removed LEVELx states from HPTW
2021-07-23 08:11:15 -04:00
Ross Thompson
00f798b37e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-22 19:42:32 -05:00
Ross Thompson
32ec457e09
Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle.
...
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
2021-07-22 19:42:19 -05:00
Kip Macsai-Goren
ee1eef3620
include SFENCE.VMA in legal instructions
2021-07-22 20:24:24 -04:00
David Harris
427063ee05
Minor unpacking cleanup
2021-07-22 17:52:37 -04:00
Ross Thompson
007812dbdc
Moved the ReadDataW register into the datapath.
...
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
00858cd401
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-22 14:05:08 -05:00
Ross Thompson
936e034be9
Fixed bug with the itlb fault not dcache ptw ready state to ready state.
2021-07-22 14:04:56 -05:00
David Harris
0822d46e97
Move Z sign swapping out of unpacker
2021-07-22 14:32:38 -04:00
David Harris
85aaa4c6d7
Move Z=0 mux out of unpacker.
2021-07-22 14:28:55 -04:00
David Harris
c04f40d6e5
Move Z=0 mux out of unpacker.
2021-07-22 14:22:28 -04:00
David Harris
625d925369
Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken.
2021-07-22 14:18:27 -04:00
David Harris
f4b45adf44
Simplify unpacker
2021-07-22 13:42:16 -04:00
David Harris
02f0c67e6f
Simplify unpacker
2021-07-22 13:40:42 -04:00
David Harris
2f23ca2b77
Removed Assumed1 from FPU interface
2021-07-22 13:04:47 -04:00
David Harris
926ffc8a15
Simplified interface to fclassify and fsgn (fixed)
2021-07-22 12:33:38 -04:00
David Harris
ae29eaa98d
Simplified interface to fclassify and fsgn
2021-07-22 12:30:46 -04:00
Ross Thompson
42fe5ceee3
Cleaned up icache and dcache.
2021-07-22 11:06:44 -05:00
Ross Thompson
89e22bc5e8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-22 10:38:24 -05:00
Ross Thompson
e907d57340
Tested all numbers of ways for dcache 1, 2, 4, and 8.
2021-07-22 10:38:07 -05:00
bbracker
9dcd5d3622
fix UART RX FIFO bug where tail pointer can overtake head pointer
2021-07-22 02:09:41 -04:00
bbracker
cdcf419147
make address translator signals visible in waveview
2021-07-21 20:07:49 -04:00
bbracker
70ef670da1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-21 20:07:03 -04:00
bbracker
3c6a1f8824
replace physical address checking with virtual address checking because address translator is broken
2021-07-21 19:47:13 -04:00
bbracker
b48d179c37
hardcoded hack to fix missing STVEC vector
2021-07-21 19:34:57 -04:00
Ross Thompson
1e88784bd4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
bb8ec549a7
fixed issue with tlbflush remaining high during a stalled sfence instruction
2021-07-21 17:43:36 -04:00
Ross Thompson
aa624625bc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:39:07 -05:00
Ross Thompson
1f0ff804cf
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 14:56:30 -05:00
Ross Thompson
511c36fb1b
Improved address bus names and usages in the walker, dcache, and tlbs.
...
Merge branch 'walkerEnhance' into main
2021-07-21 14:55:09 -05:00
Ross Thompson
abe57e3fd0
Added comment about better muxing.
2021-07-21 14:40:14 -05:00
Ross Thompson
3d79dc51bb
4 way set associative is now working.
2021-07-21 14:01:14 -05:00
Kip Macsai-Goren
e59490d032
Fixed TLB parameterization and valid bit flop to correctly do instr page faults
2021-07-21 14:44:43 -04:00
Katherine Parry
59f79722ab
FDIV and FSQRT work
2021-07-21 14:08:14 -04:00
bbracker
e8b966c5d1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-21 13:04:11 -04:00
bbracker
f7a61a5c73
progress on recovering from QEMU's errors
2021-07-21 13:00:32 -04:00
Ross Thompson
39fc9278ba
Fixed remaining bugs in 2 way set associative dcache.
2021-07-21 10:35:23 -05:00
Ross Thompson
ba3aed8760
Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux.
...
Also forgot to include cacheLRU.sv file.
2021-07-20 23:17:42 -05:00
Katherine Parry
61f81bb76e
FMA parameterized
2021-07-20 22:04:21 -04:00
Ross Thompson
8d0a552b5b
Partially working 2 way set associative d cache.
2021-07-20 17:51:42 -05:00
bbracker
d6c93a50aa
fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk
2021-07-20 17:55:44 -04:00
bbracker
b5ceb6f7c3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 15:04:13 -04:00
bbracker
945c8d496f
commented out old hack that used hardcoded addresses
2021-07-20 15:03:55 -04:00
David Harris
62b3673027
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 14:46:58 -04:00
David Harris
20744883df
flag for optional boottim
2021-07-20 14:46:37 -04:00
Ross Thompson
a042c356e1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-20 13:27:58 -05:00
Ross Thompson
bb5b5e71b1
Replaced FinalReadDataM with ReadDataM in dcache.
2021-07-20 13:27:29 -05:00
bbracker
7694342d4e
ignore mhpmcounters because QEMU doesn't implement them
2021-07-20 13:37:52 -04:00
bbracker
761300afcd
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 12:08:46 -04:00
David Harris
c117356432
Parameterized I$/D$ configurations and added sanity check assertions in testbench
2021-07-20 08:57:13 -04:00
bbracker
3de8461f3c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 05:40:49 -04:00
bbracker
c9775de3b2
testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)
2021-07-20 05:40:39 -04:00
James E. Stine
b36d6fe1be
slight mod to fpdiv - still bug in batch vs. non-batch
2021-07-20 01:47:46 -04:00
bbracker
5347a58192
major fixes to CSR checking
2021-07-20 00:22:07 -04:00
Ross Thompson
ae2371f2ce
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
Ross Thompson
07c47f0034
Restored TIM range.
2021-07-19 21:17:31 -05:00
bbracker
a01fea69dd
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 19:30:40 -04:00
bbracker
af5d319f08
change debugBuildroot because GDB formatted list is now 50 lines long per instruction (we lost 6 CSRs on the whole)
2021-07-19 19:30:29 -04:00
David Harris
678f705415
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 18:19:59 -04:00
David Harris
b2f7952b3d
Added cache configuration to config files
2021-07-19 18:19:46 -04:00
bbracker
aeaf4a31f0
MemRWM shouldn't factor into PCD checking
2021-07-19 18:03:30 -04:00
bbracker
30c381c707
create qemu_output.txt
2021-07-19 18:02:41 -04:00
bbracker
45b78dd8b3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 17:11:49 -04:00
bbracker
5911029d2b
make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways
2021-07-19 17:11:42 -04:00
Kip Macsai-Goren
3a73ae0a8b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 16:46:46 -04:00
bbracker
bb2e3b1e02
remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux
2021-07-19 16:22:05 -04:00
bbracker
78e513160e
put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests
2021-07-19 16:19:24 -04:00
bbracker
009e9d97bf
adapt testbench to removal of ReadDataWEn signal
2021-07-19 15:42:14 -04:00
bbracker
02de6014b2
adapt testbench to removal of signal
2021-07-19 15:41:50 -04:00
bbracker
76be84fa92
whoops MTIMECMP is always 64 bits
2021-07-19 15:40:53 -04:00
bbracker
fb6e618b1c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 15:13:14 -04:00
bbracker
77b690faf0
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
2021-07-19 15:13:03 -04:00
Kip Macsai-Goren
c1c564d54c
added changes to priority encoders from synthesis branch (correctly this time I hope)
2021-07-19 15:06:14 -04:00
Ross Thompson
5edd513f8c
Furture simplification of the dcache ReadDataW update.
2021-07-19 12:46:31 -05:00
Ross Thompson
5754b5f25f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-19 12:32:35 -05:00
Ross Thompson
2ee97efb9c
Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.
2021-07-19 12:32:16 -05:00
bbracker
8cbd83e804
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 13:21:04 -04:00
bbracker
2702064dda
change buildroot expectations to match reality
2021-07-19 13:20:53 -04:00
Ross Thompson
6ccbdc372d
Broken.
...
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
bbracker
986b7a8252
change sram1rw to have a small delay so that we don't have signals changing on clock edges
2021-07-19 11:30:07 -04:00
David Harris
1b55f584c7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 10:34:18 -04:00
James Stine
62b4ef6953
delete sbtm_a4 and sbtm_a5 as they are not needed
2021-07-19 08:06:00 -05:00
James Stine
892bc68918
remove sbtm3.sv - not needed
2021-07-19 08:00:53 -05:00
James Stine
55f2720f89
update part I on sbtm change
2021-07-19 07:59:27 -05:00
David Harris
0c41b8102d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 00:25:06 -04:00
Katherine Parry
8d101548f1
FDIV and FSQRT passes when simulating in modelsim
2021-07-18 23:00:04 -04:00
bbracker
64a81941ff
change memread testvectors to not left-shift bytes and half-words
2021-07-18 21:49:53 -04:00
David Harris
4729a72167
Updated FMA1 with parameterized size
2021-07-18 20:40:49 -04:00
bbracker
f4f3ef0307
linux testbench progress
2021-07-18 18:47:40 -04:00
David Harris
398e9583e9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-18 17:36:29 -04:00
David Harris
f22b6e7397
Added FLEN, NE, NF to config and started using these in FMA1
2021-07-18 17:28:25 -04:00
Katherine Parry
3527620c0b
fdivsqrt inegrated, but not completley working
2021-07-18 14:03:37 -04:00
David Harris
e31d2ef9f5
Renamed pagetablewalker to hptw
2021-07-18 04:11:33 -04:00
David Harris
e962324d00
LSUArb: Removed Demuxes on ReadDataW, DataMiisalignedM, HPTWStall
2021-07-18 03:51:30 -04:00
David Harris
40c5d3ced7
HPTW: Simpliifieid PRegEn
2021-07-18 03:35:38 -04:00
David Harris
a5a7be3e03
Removed EndWalk signal and simplified TLBMissReg
2021-07-18 03:26:43 -04:00
Ross Thompson
a0017e39e2
Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue.
2021-07-17 21:02:24 -05:00
Ross Thompson
d0ed6e250a
Fixed LRSC in 64bit version. 32bit version is broken.
2021-07-17 20:58:49 -05:00
