18 Commits

Author	SHA1	Message	Date
Jordan Carlin	f6b0805fd4	More lint cleanup: remove unused params	2024-11-16 12:35:37 -08:00
David Harris	8f09240e6c	Simplified outdated documentation pointers	2024-06-14 03:42:15 -07:00
David Harris	0419b5484a	parameterized register names in peripherals	2024-04-21 07:43:01 -07:00
Kunlin Han	8c67a76912	Remove all #delay from non-testbench.	2024-03-13 10:31:40 -07:00
David Harris	0abfe5cb55	Fixed some lint errors in derived configs	2024-01-31 11:39:59 -08:00
David Harris	f37c7bb1f6	Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this	2024-01-30 06:27:18 -08:00
David Harris	45e2317636	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
Rose Thompson	95fc5f4a1c	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
David Harris	1f2899de14	Modified rams to take USE_SRAM rather than P to facilitate synthesis	2023-11-03 05:44:13 -07:00
Ross Thompson	a89a1e675c	Merge branch 'boot' into mergeBoot ... Merges Jacob's new sdc controller into wally.	2023-07-21 17:43:45 -05:00
Ross Thompson	85567841eb	Merge branch 'testbench-params2'	2023-06-15 15:31:13 -05:00
Ross Thompson	009d8966e9	Got the srams parameterized correctly now.	2023-06-15 13:42:24 -05:00
Harshini Srinath	e227f71d46	Update ram_ahb.sv ... Program clean up	2023-06-15 10:10:38 -07:00
Ross Thompson	169539f773	Cleanup parameterization for verilator 5.010.	2023-05-31 10:02:34 -05:00
Ross Thompson	3cc85349b5	Uncore is now parameterized.	2023-05-26 16:24:12 -05:00
Jacob Pease	40f81d5da6	The Vivado-RISC-V SDC works. Wally is now booting through it.	2023-05-26 15:42:33 -05:00
Ross Thompson	46b1bca4fc	Fixed all tap/space issue in RTL.	2023-03-24 17:32:25 -05:00
David Harris	78eb90715c	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00