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454 Commits

Author SHA1 Message Date
Jordan Carlin
b76941d278
Use VCS built-in default macro instead of defining SIM_VCS 2024-06-21 15:17:59 -07:00
Rose Thompson
46ace521c6 Updated verilator makefile. 2024-06-19 16:25:31 -05:00
Ross Thompson
2d8973df1d Updated wavefile to use new names. 2024-06-19 13:57:28 -07:00
Ross Thompson
64712d2243 Updated wave to match changes in testbench. 2024-06-19 13:51:50 -07:00
Ross Thompson
ab1ee3d69b Removed *** from IFU, lrcs. 2024-06-19 09:40:35 -07:00
Jordan Carlin
00ccd80479
Update VCS RTL file exclusions with renamed ram 2024-06-18 22:47:00 -07:00
David Harris
bfd3c9fe86 Fixed gettenvval when variable is undefined per verilator Issue 5179 2024-06-14 07:09:53 -07:00
Rose Thompson
a88d5f403b Functional coverage works with wally.do 2024-05-28 14:02:54 -05:00
Rose Thompson
0c5b70c40a It's a bit hacky. But I've got functional coverage working with our wally.do script and testbench.sv. 2024-05-28 13:54:48 -05:00
Rose Thompson
48fd365b9d Still don't understand why wally.do can't load testbench.sv with functional coverage. But wally-imperas-cov.do can load testbench.sv with functional coverage. 2024-05-28 13:00:17 -05:00
Rose Thompson
4a1e856b18 Almost working functional coverage in wally.do 
riscvISACOV is now loading, but for some reason I still cannot get it to record anything.
Instead it is just logging the instructions.
 2024-05-27 18:15:12 -05:00
Rose Thompson
92ee56c1a1 Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV. 
testbench.sv was missing the trace2cov instance.
 2024-05-27 17:25:20 -05:00
Rose Thompson
4c0261fd2c Closer. Needed to reorder includes and defines. 2024-05-27 15:37:16 -05:00
Rose Thompson
ff611016c7 Closer? 2024-05-27 14:11:02 -05:00
Rose Thompson
2985cfb7eb Preliminary work to merge functional coverage into wally.do. 2024-05-27 11:59:13 -05:00
Jordan Carlin
6a2192db6e
Revert "Remove existing derived configs before creating new ones" 2024-05-23 13:56:38 -07:00
Jordan Carlin
fb8e97dd04
Remove existing derived configs before creating new ones 2024-05-23 13:17:24 -07:00
Rose Thompson
a885240fbd temporary commit to help debug merging testbench.sv with testbench-imperas.sv 2024-05-17 12:36:00 -05:00
Rose Thompson
bd8450734b Fixed more bugs with wally.do. 2024-05-17 10:39:00 -05:00
Rose Thompson
46e6459965 Updated script to run linux with imperasDV. 2024-05-14 13:46:27 -05:00
Rose Thompson
970af9551c Fixed bug with gui mode testbench_fp 
removed old wally-linux-imperas.do
 2024-05-14 13:41:20 -05:00
Rose Thompson
30bea18dec Maybe have imperasDV linux simulation merged into wally.do 2024-05-14 12:38:19 -05:00
Rose Thompson
e8f5545076 Got imperasDV running linux simulation again. 
Now need to merge do files.
 2024-05-13 16:43:13 -05:00
Rose Thompson
ceb31fec68 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-05-10 08:54:23 -05:00
Rose Thompson
b027fa44ef Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-05-10 08:53:00 -05:00
Rose Thompson
93ea5b0c1e Fixed wavefile to have function logger. 2024-05-10 08:50:42 -05:00
David Harris
04457d49f7 Updated sim-testfloat-verilator to use wsim 2024-05-10 05:03:24 -07:00
David Harris
61e559606e Fixed wsim to be able to invoke TestFloat with Verilator. However, TestFloat produces incorrect results with Verilator 2024-05-09 18:56:59 -07:00
David Harris
0d1d59a3d8 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-05-08 18:58:01 -07:00
Divya2030
eff2264752 Code Coverage Text format for each test and configuration in IndividualCovReport 2024-05-08 05:24:24 -07:00
Divya2030
b4b88c5858 VCS regression & Code Coverage 2024-05-08 04:39:42 -07:00
Divya2030
31ae18922b regression_wally vcs run works 2024-05-08 04:25:03 -07:00
David Harris
927f166e1f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-05-07 12:58:40 -07:00
Divya2030
a3f1a274d2 VCS Simulation Passed 2024-05-07 10:41:02 -07:00
David Harris
37fc45cd35 Updated Questa wally.do to terminate on a compile error 2024-05-06 11:28:00 -07:00
Divya2030
48ad4d6001 pmp coverage 2024-05-02 11:52:54 -07:00
Divya2030
3853f94337 Revert "initial commit pmp basic coverage working" 
This reverts commit 7ca1c976c0.
 2024-05-02 11:23:59 -07:00
Divya2030
7ca1c976c0 initial commit pmp basic coverage working 2024-05-02 10:33:29 -07:00
Kunlin Han
cde284d003 Fix the problem of missing sim/verilator/wkdir 2024-04-30 10:48:42 -07:00
David Harris
8f0c68373e Verilator fulladder example improvmeents 2024-04-28 22:08:00 -07:00
David Harris
1274ec55af Resolved merge conflict 2024-04-26 16:15:23 -07:00
Quswar Abid
f999ccadf4 /cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch 2024-04-26 15:55:39 -07:00
David Harris
5d97858806 Moved functional coverage files to sim/questa and to tests/riscvdv 2024-04-24 11:46:38 -07:00
David Harris
5f3676dfd7
Merge pull request #753 from quswarabid/riscvdv_bringup 
RISCVDV bringup - Coverage Collection on RISCVISACOV
 2024-04-24 09:47:34 -07:00
Quswar Abid
7b441d2881 Bringup of RISCV-DV to collect functional coverage - Update to track RV64IMAFDC_Zicsr related coverpoints from riscvISACOV 2024-04-23 18:20:29 -07:00
David Harris
0dc2c7d16a Fixed deriv path in Verilator makefile 2024-04-23 10:19:08 -07:00
David Harris
f9eec8c43f Merged wsim changes 2024-04-22 13:11:35 -07:00
Kunlin Han
9be0303493 Add support for dumping vcd. 2024-04-22 13:03:51 -07:00
David Harris
cc236bdb25 Resolved merge conflicts 2024-04-22 12:16:06 -07:00
Kunlin Han
c134b712c4
Merge branch 'main' into verilator 2024-04-22 11:35:18 -07:00