Ross Thompson
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0358a8d255
|
Merge branch 'main' into hazards
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2022-12-15 08:44:59 -06:00 |
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David Harris
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e80e84aace
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Added IDIV_ON_FPU flag to control whether integer division uses FPU
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2022-12-15 06:37:55 -08:00 |
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David Harris
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643a2e7cf9
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Use FPU divider for integer division when F is supported
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2022-12-14 17:03:13 -08:00 |
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cturek
|
482caec42d
|
Fixed BZero and initU/initUM muxes
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2022-12-14 16:44:46 +00:00 |
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Ross Thompson
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4a0e4aed99
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Signal renames to reflect figures.
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2022-12-14 09:49:15 -06:00 |
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Ross Thompson
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8f04f2d9e7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-14 09:34:34 -06:00 |
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Ross Thompson
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b69aa39f30
|
Reduced complexity of linebytemask.
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2022-12-14 09:34:29 -06:00 |
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cturek
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e4c1bb2bff
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-14 15:13:44 +00:00 |
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Ross Thompson
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0f0fed2496
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Broken dont' use.
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2022-12-11 23:24:01 -06:00 |
|
Ross Thompson
|
dbc3dac03d
|
Removed unused flushf.
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2022-12-11 16:28:11 -06:00 |
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Ross Thompson
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ad7dd56180
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Renamed CPUBusy to GatedStallF in IFU.
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2022-12-11 15:54:19 -06:00 |
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Ross Thompson
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5b38b4e639
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Renamed CPUBusy in LSU.
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2022-12-11 15:52:51 -06:00 |
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Ross Thompson
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6d573b32d2
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Changed CPUBusy to Stall in ebu modules.
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2022-12-11 15:51:35 -06:00 |
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Ross Thompson
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232f866ad1
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Renamed CPUBusy to Stall in cache.
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2022-12-11 15:49:34 -06:00 |
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Ross Thompson
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a58fbd618e
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Moved CPUBusy out of HPTW.
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2022-12-11 15:48:00 -06:00 |
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cturek
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930fcbe956
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Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
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2022-12-10 21:56:35 +00:00 |
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Ross Thompson
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d3b2e331c2
|
Added comments about why it is not possible to use FlushWay and VictimWay directly.
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2022-12-09 17:07:35 -06:00 |
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Ross Thompson
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f09b9e1572
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Finished merge of kip and ross's ifu fix.
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2022-12-09 16:52:22 -06:00 |
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Ross Thompson
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981ac3963a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-09 16:42:16 -06:00 |
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Ross Thompson
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1a24e7029f
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Minor simplification of cacheway way selection muxes.
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2022-12-09 16:42:05 -06:00 |
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Kip Macsai-Goren
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055ca9ee37
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Addded fix for 32 bit periph test and added test to regression
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2022-12-06 09:56:08 -08:00 |
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Ross Thompson
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9dd0d66ab5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-06 10:38:14 -06:00 |
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Ross Thompson
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5dbcf8fb10
|
Fixed bug Kip found.
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
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2022-12-06 10:37:45 -06:00 |
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Kip Macsai-Goren
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55627f40e2
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added passing GPIO test to 64 bit tests
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2022-12-05 21:31:00 -08:00 |
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Kip Macsai-Goren
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c6662933c4
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commented out periph test from wally32 periph so rv32ic doesn't hang
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2022-12-05 20:23:16 -08:00 |
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Kip Macsai-Goren
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4e2f4855e6
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added passing tests to regression
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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540d6c2f41
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added -01 to all WALLY tests
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2022-12-05 20:16:02 -08:00 |
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Ross Thompson
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1a9c932157
|
Renamed SelBusBuffer to SelFetchBuffer.
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2022-12-05 17:51:13 -06:00 |
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Ross Thompson
|
92066f81b6
|
Removed commented code.
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2022-12-05 17:21:56 -06:00 |
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Ross Thompson
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37551ecc43
|
Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags.
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2022-12-05 17:19:51 -06:00 |
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Ross Thompson
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dc31add951
|
Cache signal renames.
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2022-12-04 16:09:09 -06:00 |
|
Ross Thompson
|
9bf0eedf73
|
Optimized way selection logic.
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2022-12-04 12:30:56 -06:00 |
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Ross Thompson
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a130a96b45
|
Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.
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2022-12-04 01:20:51 -06:00 |
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Ross Thompson
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3dea04e644
|
Moved selectedway mux into cacheway. It makes way more sense there.
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2022-12-04 01:15:47 -06:00 |
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Ross Thompson
|
f557150cae
|
Rename LineByteMux to FetchbufferbyteSel.
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2022-12-04 01:00:04 -06:00 |
|
Ross Thompson
|
fc05e27416
|
Updated riscv arch test removed misaligned1.
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2022-12-04 00:18:10 +00:00 |
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Ross Thompson
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350fdd944d
|
Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."
This reverts commit fb221d7b64.
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2022-12-04 00:01:58 +00:00 |
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cturek
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fb221d7b64
|
Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
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2022-12-02 21:44:29 +00:00 |
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cturek
|
04ac350a29
|
Added flops to preproc
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2022-12-02 20:31:08 +00:00 |
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David Harris
|
3a07d56d33
|
Renamed FPUStallD to FCvtIntStallD
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2022-12-02 11:55:23 -08:00 |
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David Harris
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1b0f878c16
|
Renamed DivStartE to IFDivStartE
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2022-12-02 11:30:49 -08:00 |
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David Harris
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db5f3c15a4
|
FPU divider working with execute stage stall
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2022-12-02 11:11:53 -08:00 |
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David Harris
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a86c9de36b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-02 04:28:50 -08:00 |
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David Harris
|
6079a01bc8
|
update test list
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2022-12-02 04:28:47 -08:00 |
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Ross Thompson
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602d191580
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 22:36:07 -06:00 |
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David Harris
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7c3e8553d1
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 16:27:36 -08:00 |
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David Harris
|
0d23ab3ec1
|
reorder tests
|
2022-12-01 16:27:33 -08:00 |
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Ross Thompson
|
3442b04f9e
|
Properly flush cacheLRU.
|
2022-12-01 17:32:58 -06:00 |
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David Harris
|
3a8602523e
|
FPU test list
|
2022-12-01 10:18:36 -08:00 |
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Ross Thompson
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e403800ce8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 11:47:54 -06:00 |
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Ross Thompson
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5025664cb0
|
Removed unused port on cacheway.
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2022-12-01 11:47:48 -06:00 |
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David Harris
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28996d0b12
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 08:15:51 -08:00 |
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David Harris
|
1bd639be6d
|
code cleanup
|
2022-12-01 08:15:48 -08:00 |
|
Ross Thompson
|
e6bd86f4fa
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-30 17:19:04 -06:00 |
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David Harris
|
4ddc8fd603
|
signal sufixes in integer division
|
2022-11-30 15:15:37 -08:00 |
|
Ross Thompson
|
fa22484cfe
|
Reverted the IROM/DTIM address range modelsim assignment.
|
2022-11-30 17:13:33 -06:00 |
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Ross Thompson
|
2f582cd91f
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-30 13:30:37 -06:00 |
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Ross Thompson
|
a6355b1dcb
|
More optimization.
|
2022-11-30 11:26:48 -06:00 |
|
Ross Thompson
|
0aa7ce0b24
|
Removed reset on dirty cache bits.
|
2022-11-30 11:04:37 -06:00 |
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Ross Thompson
|
cedb234013
|
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
|
2022-11-30 11:01:25 -06:00 |
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Ross Thompson
|
0454eb95ad
|
Preparing to merge dirty and tag srams.
|
2022-11-30 10:40:48 -06:00 |
|
Ross Thompson
|
de538d1c2f
|
Intermediate commit. Replaced flip flop dirty bit array with sram.
|
2022-11-30 00:08:31 -06:00 |
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cturek
|
10c2d45888
|
div tests in sim-wally
|
2022-11-30 02:32:04 +00:00 |
|
Ross Thompson
|
453ea36512
|
Optimization of cacheway.
|
2022-11-29 18:30:47 -06:00 |
|
Ross Thompson
|
fbf543bf57
|
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
|
2022-11-29 17:19:31 -06:00 |
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Ross Thompson
|
0277227323
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-29 14:57:38 -06:00 |
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Ross Thompson
|
b5718c9baa
|
Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
|
2022-11-29 14:51:09 -06:00 |
|
Ross Thompson
|
96cc4c7ebe
|
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
|
2022-11-29 14:09:48 -06:00 |
|
Kip Macsai-Goren
|
c7c578c104
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-29 10:43:44 -08:00 |
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Kip Macsai-Goren
|
44ea8d8b22
|
added failing satp invalid tests to regression
|
2022-11-29 10:43:38 -08:00 |
|
Ross Thompson
|
78acd40424
|
Renamed signals in the cache.
|
2022-11-29 10:52:40 -06:00 |
|
Ross Thompson
|
6dd5668d21
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-22 18:07:32 -06:00 |
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cturek
|
bdb9e24a66
|
Almost done with Int division
|
2022-11-22 22:22:59 +00:00 |
|
cturek
|
78c2ce5649
|
Updated testbench/wave for fdivsqrt new start signals
|
2022-11-22 22:22:26 +00:00 |
|
Ross Thompson
|
279f5bc615
|
Cleanup cacheLRU.
|
2022-11-22 14:59:01 -06:00 |
|
Ross Thompson
|
e1dbe58632
|
File name change for cachereplacement policy to cacheLRU
|
2022-11-20 22:35:02 -06:00 |
|
Ross Thompson
|
4e926ba4cf
|
Signal name changes for LRU.
|
2022-11-20 22:31:36 -06:00 |
|
Ross Thompson
|
00218d559f
|
Missing a file. Last commit will fail.
|
2022-11-17 17:45:41 -06:00 |
|
Ross Thompson
|
0106777f02
|
Finally have the correct replacement policy implementation.
|
2022-11-17 17:36:37 -06:00 |
|
Ross Thompson
|
faa13a96e0
|
I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
|
2022-11-16 15:38:37 -06:00 |
|
Ross Thompson
|
22ad49eef2
|
Progress on the cache replacement policy implementation.
|
2022-11-16 15:35:34 -06:00 |
|
Ross Thompson
|
0796cd92fc
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-16 12:42:29 -06:00 |
|
Ross Thompson
|
42111db671
|
Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
|
2022-11-16 12:36:58 -06:00 |
|
David Harris
|
59335ac70f
|
comment cleanup
|
2022-11-16 10:23:20 -08:00 |
|
David Harris
|
be9c618c94
|
Renamed DivBusy to FDivBusyE in FPU
|
2022-11-16 10:13:27 -08:00 |
|
David Harris
|
128cc86254
|
Moved DivStartE to fdivsqrtfsm
|
2022-11-16 10:00:07 -08:00 |
|
Ross Thompson
|
1f21a2bab1
|
Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.
|
2022-11-16 11:15:34 -06:00 |
|
cturek
|
ffd03e9548
|
Attempt to fix FPGA synth errors
|
2022-11-15 20:34:28 +00:00 |
|
cturek
|
98b66aab9f
|
Fixed lint errors in postprocessing
|
2022-11-15 20:31:23 +00:00 |
|
Ross Thompson
|
3df51716b1
|
Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state.
|
2022-11-14 16:02:20 -06:00 |
|
Ross Thompson
|
b53f8eceef
|
Renamed Flush to FlushStage in the cache.
|
2022-11-14 14:11:05 -06:00 |
|
Ross Thompson
|
284b97aff6
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-14 13:48:56 -06:00 |
|
David Harris
|
6372139af4
|
Removed comment about nonexistent possible bug
|
2022-11-14 09:56:33 -08:00 |
|
David Harris
|
06dbed92c8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-14 09:52:24 -08:00 |
|
David Harris
|
f9202187ba
|
Removed comment about nonexistent possible bug
|
2022-11-14 09:52:21 -08:00 |
|
Ross Thompson
|
13e6f7d80b
|
Changed names of cache signals.
|
2022-11-13 21:36:12 -06:00 |
|
Ross Thompson
|
788ae5fb18
|
Updated wave file.
|
2022-11-13 21:34:45 -06:00 |
|
cturek
|
abaa33b92a
|
Added majority of combinational logic
|
2022-11-14 00:06:38 +00:00 |
|
cturek
|
6740d77b63
|
Added Quotient/Remainder calcs to normal termination
|
2022-11-13 23:44:34 +00:00 |
|
cturek
|
12e3646153
|
Added flops for n and m, added B=0 signal
|
2022-11-13 23:02:43 +00:00 |
|