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523 Commits

Author SHA1 Message Date
Kip Macsai-Goren
8823339aef added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet 2021-07-23 16:02:42 -04:00
Kip Macsai-Goren
0653630d29 added sfence to legal instructions, zeroed out rom file to populate for tests 2021-07-23 15:55:08 -04:00
Kip Macsai-Goren
f02d52ce50 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-23 15:16:01 -04:00
bbracker
71ef87bc55 testbench workaround for QEMU's SSTATUS XLEN bits 2021-07-23 14:00:44 -04:00
Kip Macsai-Goren
ee1eef3620 include SFENCE.VMA in legal instructions 2021-07-22 20:24:24 -04:00
David Harris
625d925369 Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken. 2021-07-22 14:18:27 -04:00
bbracker
70ef670da1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-21 20:07:03 -04:00
bbracker
3c6a1f8824 replace physical address checking with virtual address checking because address translator is broken 2021-07-21 19:47:13 -04:00
Katherine Parry
59f79722ab FDIV and FSQRT work 2021-07-21 14:08:14 -04:00
Katherine Parry
61f81bb76e FMA parameterized 2021-07-20 22:04:21 -04:00
bbracker
d6c93a50aa fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk 2021-07-20 17:55:44 -04:00
bbracker
b5ceb6f7c3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 15:04:13 -04:00
bbracker
945c8d496f commented out old hack that used hardcoded addresses 2021-07-20 15:03:55 -04:00
David Harris
62b3673027 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 14:46:58 -04:00
David Harris
20744883df flag for optional boottim 2021-07-20 14:46:37 -04:00
bbracker
7694342d4e ignore mhpmcounters because QEMU doesn't implement them 2021-07-20 13:37:52 -04:00
bbracker
761300afcd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 12:08:46 -04:00
David Harris
c117356432 Parameterized I$/D$ configurations and added sanity check assertions in testbench 2021-07-20 08:57:13 -04:00
bbracker
c9775de3b2 testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr) 2021-07-20 05:40:39 -04:00
bbracker
5347a58192 major fixes to CSR checking 2021-07-20 00:22:07 -04:00
bbracker
aeaf4a31f0 MemRWM shouldn't factor into PCD checking 2021-07-19 18:03:30 -04:00
bbracker
5911029d2b make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways 2021-07-19 17:11:42 -04:00
bbracker
009e9d97bf adapt testbench to removal of ReadDataWEn signal 2021-07-19 15:42:14 -04:00
bbracker
02de6014b2 adapt testbench to removal of signal 2021-07-19 15:41:50 -04:00
bbracker
77b690faf0 make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset 2021-07-19 15:13:03 -04:00
Katherine Parry
8d101548f1 FDIV and FSQRT passes when simulating in modelsim 2021-07-18 23:00:04 -04:00
bbracker
f4f3ef0307 linux testbench progress 2021-07-18 18:47:40 -04:00
Katherine Parry
3527620c0b fdivsqrt inegrated, but not completley working 2021-07-18 14:03:37 -04:00
Ross Thompson
a0017e39e2 Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue. 2021-07-17 21:02:24 -05:00
David Harris
c29a2ff8df Started atomics 2021-07-17 21:11:41 -04:00
bbracker
6feb95c779 swapped out linux testbench signal names 2021-07-17 14:48:12 -04:00
David Harris
9741b01465 hptw: minor cleanup 2021-07-17 13:40:12 -04:00
David Harris
37cc2ca30f hptw: factored pregen 2021-07-17 11:11:10 -04:00
David Harris
622a14cbdd Removed more unused signals from ahblite 2021-07-17 02:21:54 -04:00
Kip Macsai-Goren
3d14d573a0 included virtual memory tests in testbench 2021-07-16 17:57:24 -04:00
Ross Thompson
965f34d78f Added guide for Ben to do linux conversion. 2021-07-16 15:04:30 -05:00
Ross Thompson
abce241f68 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
96aa106852 Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
4549a9f1c9 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
c39a228266 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. 2021-07-15 11:00:42 -05:00
Ross Thompson
f234875779 dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
6163629204 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
701ea38964 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
d3a1a2c90a Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Ross Thompson
771c7ff130 Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
278bbfbe3c Partially working changes to support uncached memory access. Not sure what CommitedM is. 2021-07-13 17:24:59 -05:00
Katherine Parry
acdd2e4504 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
Ross Thompson
d3ffbe0e5d Modularized the shadow memory to reduce performance hit. 2021-07-13 10:55:57 -05:00
Ross Thompson
17dc488010 Got the shadow ram cache flush working. 2021-07-13 10:03:47 -05:00
Ross Thompson
9fe6190763 Team work on solving the dcache data inconsistency problem. 2021-07-12 23:46:32 -05:00
Ross Thompson
6b42b93886 Now updates the dtim with the dirty data in the dcache. 
Simulation is showing issues.  It lookslike the cache is not
evicting the correct data.
 2021-07-12 15:13:27 -05:00
Ross Thompson
8ca8b9075d Progress towards the test bench flush. 2021-07-12 14:22:13 -05:00
Katherine Parry
0cc07fda1b Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
bbracker
0e708a72f3 more completely uncomment MMU tests to make sim wally work 2021-07-06 14:33:52 -04:00
Kip Macsai-Goren
770420b448 added new mmu tests to makefrag and commented out in the testbench 2021-07-05 10:54:30 -04:00
David Harris
e65fb5bb35 Added F_SUPPORTED flag to disable floating point unit when not in MISA 2021-07-05 10:30:46 -04:00
David Harris
c897bef8cd Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
Ben Bracker
9709bd78e1 stop busybear from hanging 2021-07-02 17:22:09 -05:00
bbracker
9927f771cc linux testbench now ignores HWRITE glitches caused by flush glitches 2021-06-25 09:28:52 -04:00
bbracker
2694a7a43f made testbench-linux's PCDwrong be FlushD 2021-06-25 08:15:19 -04:00
Katherine Parry
bc8d660bc5 FPU forwarding reworked pt.1 2021-06-24 18:39:18 -04:00
bbracker
55cf205222 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-24 01:42:41 -04:00
bbracker
b84419ff4e overhauled linux testbench and spoofed MTTIME interrupt 2021-06-24 01:42:35 -04:00
Katherine Parry
44af47608c fpu clean-up 2021-06-23 16:42:40 -04:00
Katherine Parry
9eb6eb40bf rv64f FLW passes imperas tests 2021-06-22 16:36:16 -04:00
David Harris
82515862e3 Commented out 100k tests to improve speed 2021-06-21 01:43:18 -04:00
David Harris
aef408af58 Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
bbracker
5afad80432 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-20 22:29:40 -04:00
bbracker
665a67f442 linux actually uses FPU now! 2021-06-20 22:29:21 -04:00
Katherine Parry
26bad083ad all rv64f instructions except convert, divide, square root, and FLD pass 2021-06-20 20:24:09 -04:00
bbracker
1f2a967e0f read from MSTATUS workaround because QEMU has incorrect MSTATUS 2021-06-20 10:11:39 -04:00
bbracker
2611d214a6 testbench update b/c QEMU extends 32b CSRs to 64b 2021-06-20 09:24:19 -04:00
bbracker
9469367da3 make buildroot ignore SSTATUS because QEMU did not originally log it 2021-06-20 05:31:24 -04:00
bbracker
78f4703dc9 MSTATUS workaround 2021-06-20 04:48:09 -04:00
bbracker
927d99cf3b workaround for ignoring MTIME 2021-06-20 02:26:39 -04:00
bbracker
3e32ba3684 make buildroot waves only turn on after a user-specified point 2021-06-20 00:39:30 -04:00
bbracker
f84a689c19 fixed PCtext error by using blocking assignments 2021-06-18 17:37:40 -04:00
bbracker
958f60c704 restore graphical buildroot sim 2021-06-18 11:58:16 -04:00
bbracker
8ae333a6b2 remove unused testbench-busybear.sv 2021-06-18 08:15:19 -04:00
David Harris
72d8d34e3c allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
e03912f64c Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
bbracker
832e4fc7e3 making linux waveforms more useful 2021-06-17 08:37:37 -04:00
bbracker
e93e528aa1 changed parsedCSRs2] to parsedCSRs 2021-06-17 05:18:14 -04:00
David Harris
9dd3857c26 Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
David Harris
cfe5c27946 Resized BOOT TIM to 1 KB 2021-06-08 14:04:32 -04:00
bbracker
17960a6484 Ah big ole merge! Passes sim-wally-batch and linting, so should be fine 2021-06-08 12:41:25 -04:00
bbracker
5026a42fac * GPIO comprehensive testing 
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
 2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
46b2b19792 implemented simpler page mixers, cleaned up a bit 2021-06-07 18:32:34 -04:00
David Harris
b37bcc8e38 Continued merge 2021-06-07 12:49:47 -04:00
David Harris
1e67db2f0c Second attept to commit refactoring config files 2021-06-07 12:37:46 -04:00
David Harris
95cc70295b Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
Katherine Parry
e4db6ea6f5 fixed lint warnings for fpu and lzd 2021-06-05 12:06:33 -04:00
Kip Macsai-Goren
b99b5f8e0e moved privilege dfinitions into wally-constants, upgraded relevant includes 2021-06-04 17:55:07 -04:00
Katherine Parry
19116ed889 Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
Kip Macsai-Goren
a84dd6dfc5 added tests for SV48 and translation off with vmem 2021-06-03 14:28:52 -04:00
James E. Stine
bccdd2c137 Updates to muldiv.sv for 32-bit div/rem 2021-06-01 15:31:07 -04:00
Ross Thompson
8f9680556f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 11:33:12 -05:00
Ross Thompson
5bc2a8b346 Now have global history working correctly. 2021-06-01 10:57:43 -05:00
James E. Stine
927aec34a2 Modify muldiv.sv to handle W instructions for 64-bits 2021-05-31 23:27:42 -04:00
bbracker
a45b61ede9 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
Katherine Parry
0646e08609 classify unit created and passes imperas tests 2021-05-27 18:53:55 -04:00
Katherine Parry
65eca433b6 All compare instructions pass imperas tests 2021-05-27 15:23:28 -04:00
Katherine Parry
bd05de0dbb FADD and FSUB imperas tests pass 2021-05-26 12:33:33 -04:00
Kip Macsai-Goren
ba134eb166 partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields 2021-05-24 20:59:26 -04:00
James E. Stine
1704fdc877 Mod for DIV/REM instruction and update to div.sv unit 2021-05-24 19:29:13 -05:00
Ross Thompson
3c5e87d6c2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-24 14:28:41 -05:00
Katherine Parry
03aea055fa FMV.X.D imperas test passes 2021-05-24 14:44:30 -04:00
Ross Thompson
daf344f1ba Updated branch predictor tests/benchmarks. 2021-05-24 11:13:33 -05:00
Katherine Parry
55f22979ca FSD and FLD imperas tests pass 2021-05-23 18:33:14 -04:00
bbracker
142b02b30a improved PLIC test organization 2021-05-21 15:13:02 -04:00
James E. Stine
49a4097d97 Minor testbench updates to rv64icfd 2021-05-21 09:41:21 -05:00
James E. Stine
47487a625f Update to testbench-imperase for rv64icfd 2021-05-21 09:28:44 -05:00
James E. Stine
694e21541b Update to FLD/FSD testbench 2021-05-21 09:26:55 -05:00
James E. Stine
474d479280 Update to rv64icfd wally-config to run through FP tests 2021-05-21 09:22:17 -05:00
Katherine Parry
67a41748ba FMV.D.X imperas test passes 2021-05-20 22:18:33 -04:00
Katherine Parry
71e4a10efb FMV.D.X imperas test passes 2021-05-20 22:17:59 -04:00
bbracker
114bba8370 small bit of busybear debug progress 2021-05-19 20:18:00 -04:00
bbracker
fd4fae0406 commented out MSTATUS test 2021-05-19 12:38:01 -04:00
James E. Stine
f407bee5ae Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA) 2021-05-18 13:48:44 -05:00
David Harris
7dcc53dcf5 fixed rv64mmu makefile 2021-05-18 14:25:55 -04:00
Katherine Parry
409438bc95 floating point infinite loop removed from imperas tests 2021-05-18 10:42:51 -04:00
bbracker
86d55cd07a fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions 2021-05-17 19:25:54 -04:00
bbracker
69ef758e78 regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench 2021-05-17 18:44:47 -04:00
James E. Stine
41da78e0b6 Mod Imperas Testbench for updated Div/Rem 2021-05-17 16:56:30 -05:00
Domenico Ottolia
1c884338b0 Forgot to add csr permission tests to testbench 2021-05-04 20:20:22 -04:00
ushakya22
6274c8cb80 Added mip tests to testbench 2021-05-04 15:36:06 -04:00
Domenico Ottolia
14becde792 Re-add medeleg tests to testbench 2021-05-04 14:42:20 -04:00
ushakya22
da352c81e7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 02:22:17 -04:00
ushakya22
66344f0604 Added MIE tests to testbench 2021-05-04 02:22:01 -04:00
Domenico Ottolia
2c39c0a6a5 Minor tweaks to mcause & scause tests 2021-05-04 01:33:49 -04:00
David Harris
7c2481bea6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 01:19:57 -04:00
David Harris
4db3780ebb Fixed testbench to produce error when signature.output doesn't exist 2021-05-04 01:19:44 -04:00
Thomas Fleming
39135f221e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 01:14:13 -04:00
Domenico Ottolia
1556cc5b9f Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE 2021-05-04 01:04:12 -04:00
Domenico Ottolia
84911e6345 Fix 32 bit privileged tests!!! 2021-05-04 00:16:19 -04:00
Thomas Fleming
4f5ef65aeb Restore original order of tests 2021-05-03 23:50:21 -04:00
Thomas Fleming
d53afc8510 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 23:15:39 -04:00
Thomas Fleming
1f6db293fa Enable mmu tests in testbench 2021-05-03 23:15:23 -04:00
Domenico Ottolia
12d8ff617b Run all tests 2021-05-03 22:38:59 -04:00
Domenico Ottolia
353d4e9238 Update cause tests to be longer 2021-05-03 22:38:26 -04:00
Domenico Ottolia
db4e447a25 Add mtvec and stvec tests to testbench 2021-05-03 22:19:50 -04:00
Shriya Nadgauda
c10d332c6e working testbench-imperas 2021-05-03 22:16:58 -04:00
Shriya Nadgauda
0be6b81df9 finishing merge conflict changes 2021-05-03 22:15:05 -04:00
Shriya Nadgauda
52e0b703b7 merge conflict fixes 2021-05-03 22:12:30 -04:00
Shriya Nadgauda
0282aebec7 updated pipeline tests 2021-05-03 22:07:36 -04:00
Elizabeth Hedenberg
08bfaeffe3 coremark print statment 2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
800f799b7c coremark updates 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
81ed9b5d06 coremark directory changes 2021-05-03 19:35:06 -04:00
David Harris
699a8f3ac3 Extended maximum signature length to 1M 2021-05-03 15:29:20 -04:00