Rose Thompson
f11f88ac2b
Updates to tlb to check access permissions for cbo*
2023-11-29 16:20:43 -06:00
Rose Thompson
f4e4aac8b5
Added CMOp to pmp checker
2023-11-29 16:09:31 -06:00
Rose Thompson
fc04b6f7d8
Removed redundant ZICBOM/Z_SUPPORTED from pmachecker.
2023-11-29 15:39:39 -06:00
Rose Thompson
053b094620
Simpilified pmachecker for cmo.
2023-11-29 12:26:18 -06:00
Rose Thompson
9a24a5d957
Renamed signal in pmachecker.
2023-11-28 00:05:12 -06:00
Rose Thompson
9290c3f957
Added correct cbo fault behavior.
2023-11-27 20:57:33 -06:00
Rose Thompson
beb95dd592
Modified the pmachecker to correctly check the permissions for cmo instructions.
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However this isn't fully tested.
2023-11-27 17:44:11 -06:00
Rose Thompson
b74bfbeefd
Merge branch 'main' into Zicclsm
2023-11-10 16:15:32 -06:00
naichewa
a08356fdaa
correct exclusion tags and reset testbench
2023-11-01 10:34:39 -07:00
Rose Thompson
2241976d29
Updated mmu to not generate trap on cacheable misaligned access when supported.
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Updated tests with David's help.
2023-10-30 18:26:11 -05:00
naichewa
d5d4f9d044
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
David Harris
19a6bbb01b
UpdateDA cleanup: don't assert UpdateDA when there is no SVADU
2023-10-04 09:57:13 -07:00
David Harris
d526d28804
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
David Harris
9747d122d2
tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
2023-09-02 12:56:36 -07:00
David Harris
e75ceb044f
Improved tlb and controller coverage; fixed exclusions on broken lines
2023-08-31 00:27:47 -07:00
David Harris
8d3ff59673
Completed basic tests of svnapot and svpbmt
2023-08-28 06:57:35 -07:00
David Harris
f7b50f4721
Preparing to merge with CBO* changes
2023-08-25 18:41:03 -07:00
David Harris
bd6eef2a51
Initial implementation of SVNAPOT and SVPBMT does not break regression
2023-08-25 18:33:08 -07:00
David Harris
c6631ef808
Added N and PBMT bits to MMU PTE
2023-08-24 19:44:46 -07:00
Ross Thompson
b1f7a5768f
Removed all old references to the old flash card controller.
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Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
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Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
c0966c32e5
Improved critical path.
2023-07-19 14:59:37 -05:00
Ross Thompson
4c4eb080ee
RTL changes for Xcelium.
2023-07-11 10:51:02 -05:00
Ross Thompson
85567841eb
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
b8a243827b
Found a whole bunch of files still using the old `define configurations.
2023-06-15 13:09:07 -05:00
Harshini Srinath
a1a9d668c5
Update pmpchecker.sv
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Program clean up
2023-06-12 18:44:36 -07:00
Harshini Srinath
09ac5b1817
Update pmpadrdec.sv
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Program clean up
2023-06-12 18:41:47 -07:00
Harshini Srinath
ccb81c84f4
Update pmachecker.sv
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Program clean up
2023-06-12 18:39:36 -07:00
Harshini Srinath
5a6a932b7e
Update mmu.sv
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Program clean up
2023-06-12 18:36:04 -07:00
Harshini Srinath
a57a619349
Update hptw.sv
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Program clean up
2023-06-12 18:31:38 -07:00
Harshini Srinath
ec0454111f
Update adrdecs.sv
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Program clean up
2023-06-12 18:22:32 -07:00
Harshini Srinath
b1ee6bfde5
Update adrdec.sv
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Program clean up
2023-06-12 17:28:21 -07:00
Ross Thompson
a963f0af3a
Updated source code to be compatible with verilator 5.011 for lint only.
2023-05-31 10:44:23 -05:00
Ross Thompson
8e1476cb8c
Possible fix for Linux bug and bug 203. ImperasDV mismatches in linux boot around 571M instructions after the login prompt.
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This bug occurs when there are back to back HPTW requests and the first generates an access fault during the walk. The old implementation uses a delayed version of the fault to prevent the HTPW fsm from transitioning out of the IDLE state. Because the first request generates the fault and the second request is pipelined the second request appears as if it also faults so the FSM does not perform the walk.
The new implementation adds a FAULT state. When the HPTW generates an access fault it transitions to this state removes the HPTWStall and then transitions to IDLE. There may still be a remaining bug here if the pipeline is stalled for another reason. However I don't think it is possible by construction. The only possible sources of stalls at this point would be IFU and LSU stalls and both are required to make this condition happen.
2023-05-30 15:20:24 -05:00
Jacob Pease
40f81d5da6
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Ross Thompson
02a788a083
PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue.
2023-05-26 11:06:48 -05:00
Ross Thompson
0020d94b39
Updated mmu's tlb and hptw to use Lim's parameterization.
2023-05-24 18:02:22 -05:00
Ross Thompson
70c8828ac2
PM(P/A) checkers parameterized based on Lim's work.
2023-05-24 17:20:55 -05:00
Ross Thompson
fcb1c63f5f
Partial parameterization into mmu.
2023-05-24 16:12:41 -05:00
David Harris
d5b718be38
IMMU exclude non word-sized accesses
2023-05-01 08:14:19 -07:00
David Harris
6253c042b2
Merged coverage exclusions for PMP
2023-04-28 08:04:25 -07:00
David Harris
194b848fbf
PMA Checker coverage
2023-04-28 07:53:59 -07:00
David Harris
af7959a3e2
Commenting
2023-04-28 07:52:08 -07:00
David Harris
9843223ddd
Removed clear from TLBLRU because there is no need to flush LRU state and it causes coverage issues
2023-04-28 07:03:46 -07:00
Liam
4d8eafd27d
Pmpadrdecs test cases changing AdrMode to 2 or 3
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Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
2023-04-27 12:23:35 -07:00
Limnanthes Serafini
034c289a36
Misc typo and indent fixing.
2023-04-13 16:54:15 -07:00
Ross Thompson
e531b0103e
Fixed wally64/32priv test hangup.
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The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
2023-04-05 23:13:45 -05:00
Ross Thompson
394f2d65f2
Progress on bug 203.
2023-04-05 13:20:04 -05:00
David Harris
2e5c50e24a
Fixed RV32 tests after PMP fix
2023-03-28 08:35:23 -07:00
David Harris
e8904411ce
Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
2023-03-28 06:58:17 -07:00
