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Author SHA1 Message Date
David Harris
057ee56d7e Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv 2022-03-29 19:16:41 +00:00
David Harris
049c55769a fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
Kip Macsai-Goren
ad106e7130 made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes 2022-03-29 02:26:42 +00:00
Kip Macsai-Goren
c32f5e9cee fixed signature location of the new periph with no compressed instructions 2022-03-29 02:15:17 +00:00
bbracker
46ffa4b079 fix typo that Madeleine found 2022-03-28 15:39:29 -07:00
Ross Thompson
b3506c755a test. 2022-03-28 17:04:58 -05:00
bbracker
b5b9eedf33 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-28 13:41:14 -07:00
bbracker
6fc54435c5 checkpointSweep is bash-specific, so add shebang to make it so 2022-03-28 13:40:50 -07:00
Kip Macsai-Goren
dc9635b757 fixed double multiplication on vectored interrupts 2022-03-28 19:12:31 +00:00
Kip Macsai-Goren
2e68ab7bb4 added test config that doesn't use compressed instructions for privileged tests 2022-03-28 19:12:31 +00:00
Ross Thompson
f818b2a428 Updated debug2.xdc ila constraints to match rtl. 2022-03-28 10:52:26 -05:00
Ross Thompson
63e01b65c2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-28 10:23:25 -05:00
Ross Thompson
dc74a6ba9c Temporary change of plic uart id to 10. 2022-03-28 10:23:20 -05:00
bbracker
2900117341 fix genCheckpoint.sh binary memory dump 2022-03-27 20:54:59 -07:00
bbracker
6b812f33e1 change genCheckpoint.sh to only log 128MB of RAM 2022-03-27 19:16:39 -07:00
bbracker
284f1ab75e fix parseGDBtoTrace.py to expect the CSRs that QEMU actually prints out 2022-03-27 19:05:44 -07:00
bbracker
d1e4b61aa3 refactored buildroot configuration 2022-03-27 15:13:03 -07:00
bbracker
6b2474a306 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-27 15:11:42 -07:00
bbracker
3dcb87473b change devicetree to expect only 128MB of RAM 2022-03-27 15:11:36 -07:00
Skylar Litz
29d1f64588 add AtemptedInstructionCount signal 2022-03-26 21:28:57 +00:00
Skylar Litz
bb8587e06f update to match new filesystem organization 2022-03-26 21:28:32 +00:00
Kip Macsai-Goren
8cde06b886 added basic trap tests that do not pass regression yet. updated signature adresses 2022-03-25 22:57:41 +00:00
Ross Thompson
7099259ff7 I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit. 2022-03-25 13:10:31 -05:00
Ross Thompson
abf66ff85f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-25 11:01:01 -05:00
Ross Thompson
7a824eaae1 Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB. 2022-03-24 23:47:28 -05:00
bbracker
b08066381a fix multiple-context PLIC checkpoint generation 2022-03-25 01:02:22 +00:00
bbracker
150a7b234b tabs vs spaces disagreement 2022-03-24 17:11:41 -07:00
bbracker
9f60256f22 1st attempt at multiple channel PLIC 2022-03-24 17:08:10 -07:00
Ross Thompson
58668812c1 Moved WriteDataM register into LSU. 2022-03-23 14:17:59 -05:00
Ross Thompson
07b7dbc922 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-23 14:10:38 -05:00
Katherine Parry
abdbc31d14 fixed typo in unpack.sv 2022-03-23 18:26:59 +00:00
Ross Thompson
c55c5eec82 Another change required for forcing to work correctly with MIE/MIP and SIE/SIP. 2022-03-23 10:26:17 -05:00
Ross Thompson
f1787670d4 Cleanup in testbench-linux.sv. 2022-03-22 22:34:38 -05:00
Ross Thompson
6c9750c725 reverted temporary change to configs. 2022-03-22 22:31:34 -05:00
Katherine Parry
ead88fba55 fixed lint error in fpudivsqrtrecur.sv 2022-03-23 03:24:41 +00:00
Ross Thompson
6ab14d7302 Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing. 2022-03-22 22:04:06 -05:00
Ross Thompson
600a97982f Reverted change to configuration which caused issue with lint. 2022-03-22 21:44:08 -05:00
Ross Thompson
c5be2cb1d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-22 21:28:50 -05:00
Ross Thompson
7fc128ba7c added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP. 2022-03-22 21:28:34 -05:00
Katherine Parry
c3c764a171 unpack.sv cleanup 2022-03-23 01:53:37 +00:00
Ross Thompson
80d376877a Added spoof of uart addresses +0x2 and +0x6. 2022-03-22 16:52:27 -05:00
Ross Thompson
cec7625d91 Added comment about needed fix to misaligned fault. 2022-03-22 16:52:07 -05:00
Katherine Parry
2042374102 FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
Ross Thompson
d347de8c49 dtim writes are supressed on non cacheable operation. 2022-03-12 00:46:11 -06:00
Ross Thompson
d8947fa616 cleanup of ram.sv 2022-03-11 18:09:22 -06:00
Ross Thompson
69a6a4800e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-11 15:42:10 -06:00
Ross Thompson
d68446cf92 Added new asserts to testbench. 2022-03-11 15:41:53 -06:00
Ross Thompson
e802deb4d6 Can now support the following memory and bus configurations. 
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
 2022-03-11 15:18:56 -06:00
Ross Thompson
3dbf6790e1 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Kip Macsai-Goren
6ac9a626e2 added preliminary files for trap/priv tests. These DO NOT pass make yet because if interrrupt handling problems 2022-03-11 20:00:54 +00:00